This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
[committed] Fix compile/simd-5.c for mips16
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 07 May 2004 16:04:54 +0100
- Subject: [committed] Fix compile/simd-5.c for mips16
This patch fixes an ICE in compile/simd-5.c at -O0 for 64-bit mips16 targets.
The testcase has the following multiplication:
(parallel [(set (subreg:SI (reg:V2SI 184) 0)
(mult:SI (reg:SI 3 185)
(reg:SI 2 186)))
(clobber (scratch:SI))])
and reg 184 doesn't get allocated a hard register. Since the subreg is
a subword lowpart of a word-sized register, the WORD_REGISTER_OPERATIONS
code in push_reload() decides to reload the inner register, (reg:V2SI 184).
This ought to be fine, but the backend currently stops LO and HI from
storing anything other than true integer modes. Relaxing the check from
class == MODE_INT to INTEGRAL_MODE_P allows them to store vector modes too.
I don't think there's anything mips16-specific about this. It's just that,
by having fewer registers, mips16 is more likely to need a LO->stack reload.
Tested on mips64vrel-elf, mips-sgi-irix6.5 and mips64el-linux-gnu.
Applied to head.
Richard
* config/mips/mips.c (override_options): Allow the hi and lo registers
to store any integral mode, not just MODE_INTs.
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.411
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.411 mips.c
--- config/mips/mips.c 6 May 2004 15:27:17 -0000 1.411
+++ config/mips/mips.c 6 May 2004 20:21:17 -0000
@@ -4970,7 +4990,7 @@ override_options (void)
|| (ISA_HAS_8CC && mode == TFmode));
else if (MD_REG_P (regno))
- temp = (class == MODE_INT
+ temp = (INTEGRAL_MODE_P (mode)
&& (size <= UNITS_PER_WORD
|| (regno == MD_REG_FIRST
&& size == 2 * UNITS_PER_WORD)));