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[trivial PATCH, commited]: Move atan?f2 expanders near atan2?f3 expanders

Hello!

This patch just moves atan2 expanders to better place. This trivial
patch is part of patch, approved at
http://gcc.gnu.org/ml/gcc-patches/2004-04/msg01587.html

Patch introduces no functional changes, and was tested by bootstrapping
gcc on i686-pc-linux-gnu.

2004-04-30 Uros Bizjak <uros@kss-loka.si>

          * config/i386/i386.md (atansf2, atandf2, atanxf2): Move near
          atan2?f3 expanders.

Uros.



Index: gcc/config/i386/i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.530
diff -u -p -r1.530 i386.md
--- gcc/config/i386/i386.md	29 Apr 2004 07:19:25 -0000	1.530
+++ gcc/config/i386/i386.md	30 Apr 2004 05:38:46 -0000
@@ -15235,6 +15235,19 @@
   DONE;
 })
 
+(define_expand "atandf2"
+  [(parallel [(set (match_operand:DF 0 "register_operand" "")
+		   (unspec:DF [(match_dup 2)
+			       (match_operand:DF 1 "register_operand" "")]
+		    UNSPEC_FPATAN))
+	      (clobber (match_scratch:DF 3 ""))])]
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+   && flag_unsafe_math_optimizations"
+{
+  operands[2] = gen_reg_rtx (DFmode);
+  emit_move_insn (operands[2], CONST1_RTX (DFmode));  /* fld1 */
+})
+
 (define_insn "atan2sf3_1"
   [(set (match_operand:SF 0 "register_operand" "=f")
         (unspec:SF [(match_operand:SF 2 "register_operand" "0")
@@ -15260,6 +15273,19 @@
   DONE;
 })
 
+(define_expand "atansf2"
+  [(parallel [(set (match_operand:SF 0 "register_operand" "")
+		   (unspec:SF [(match_dup 2)
+			       (match_operand:SF 1 "register_operand" "")]
+		    UNSPEC_FPATAN))
+	      (clobber (match_scratch:SF 3 ""))])]
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+   && flag_unsafe_math_optimizations"
+{
+  operands[2] = gen_reg_rtx (SFmode);
+  emit_move_insn (operands[2], CONST1_RTX (SFmode));  /* fld1 */
+})
+
 (define_insn "atan2xf3_1"
   [(set (match_operand:XF 0 "register_operand" "=f")
         (unspec:XF [(match_operand:XF 2 "register_operand" "0")
@@ -15285,6 +15311,19 @@
   DONE;
 })
 
+(define_expand "atanxf2"
+  [(parallel [(set (match_operand:XF 0 "register_operand" "")
+		   (unspec:XF [(match_dup 2)
+			       (match_operand:XF 1 "register_operand" "")]
+		    UNSPEC_FPATAN))
+	      (clobber (match_scratch:XF 3 ""))])]
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+   && flag_unsafe_math_optimizations"
+{
+  operands[2] = gen_reg_rtx (XFmode);
+  emit_move_insn (operands[2], CONST1_RTX (XFmode));  /* fld1 */
+})
+
 (define_expand "asindf2"
   [(set (match_dup 2)
 	(float_extend:XF (match_operand:DF 1 "register_operand" "")))
@@ -15942,45 +15981,6 @@
   for (i=2; i<9; i++)
     operands[i] = gen_reg_rtx (XFmode);
   emit_move_insn (operands[6], CONST1_RTX (XFmode));  /* fld1 */
-})
-
-(define_expand "atansf2"
-  [(parallel [(set (match_operand:SF 0 "register_operand" "")
-		   (unspec:SF [(match_dup 2)
-			       (match_operand:SF 1 "register_operand" "")]
-		    UNSPEC_FPATAN))
-	      (clobber (match_scratch:SF 3 ""))])]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations"
-{
-  operands[2] = gen_reg_rtx (SFmode);
-  emit_move_insn (operands[2], CONST1_RTX (SFmode));  /* fld1 */
-})
-
-(define_expand "atandf2"
-  [(parallel [(set (match_operand:DF 0 "register_operand" "")
-		   (unspec:DF [(match_dup 2)
-			       (match_operand:DF 1 "register_operand" "")]
-		    UNSPEC_FPATAN))
-	      (clobber (match_scratch:DF 3 ""))])]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations"
-{
-  operands[2] = gen_reg_rtx (DFmode);
-  emit_move_insn (operands[2], CONST1_RTX (DFmode));  /* fld1 */
-})
-
-(define_expand "atanxf2"
-  [(parallel [(set (match_operand:XF 0 "register_operand" "")
-		   (unspec:XF [(match_dup 2)
-			       (match_operand:XF 1 "register_operand" "")]
-		    UNSPEC_FPATAN))
-	      (clobber (match_scratch:XF 3 ""))])]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations"
-{
-  operands[2] = gen_reg_rtx (XFmode);
-  emit_move_insn (operands[2], CONST1_RTX (XFmode));  /* fld1 */
 })
 
 ;; Block operation instructions
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