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[Patch] [PPC] Convert peephole to peephole2

From: Andrew Pinski <pinskia at physics dot uc dot edu>
To: "gcc-patches at gcc dot gnu dot org Patches" <gcc-patches at gcc dot gnu dot org>
Cc: Andrew Pinski <pinskia at physics dot uc dot edu>
Date: Wed, 28 Apr 2004 11:35:41 -0400
Subject: [Patch] [PPC] Convert peephole to peephole2

Since the consensus is move away from peephole to peephole2, this patch does this for a simple one in the RS6000 backend, lfq/stq. This patch follows what the sparc backend does for its peepholes like this.

OK? Bootstrapped on powerpc-apple-darwin7.3.0 and checked to see code is still uses lfq/stq. I have had this patch in my local tree for a while now.

Thanks,
Andrew Pinski

ChangeLog:

	* config/rs6000/rs6000.c (registers_ok_for_quad_peep):
	Return false if we have pseudo registers.
	(addrs_ok_for_quad_peep): Rename to ...
	(mems_ok_for_quad_peep): this.
	Add check for volatile memory.
	* config/rs6000/rs6000-protos.h (addrs_ok_for_quad_peep):
	Rename to ...
	(mems_ok_for_quad_peep): this.
	* config/rs6000/rs6000.md: Change peephole's for lfq/stq
	to peephole2's.
	(lfq_power2): New instruction.
	(stfq_power2): Likewise.


Patch:
Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.630
diff -p -c -3 -r1.630 rs6000.c
*** rs6000.c	24 Apr 2004 06:37:18 -0000	1.630
--- rs6000.c	28 Apr 2004 15:15:30 -0000
*************** includes_rldicr_lshift_p (rtx shiftop, r
*** 8594,8603 ****
  }

  /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
!    for lfq and stfq insns.
!
!    Note reg1 and reg2 *must* be hard registers.  To be sure we will
!    abort if we are passed pseudo registers.  */

  int
  registers_ok_for_quad_peep (rtx reg1, rtx reg2)
--- 8594,8600 ----
  }

  /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
!    for lfq and stfq insns iff the registers are hard registers.   */

  int
  registers_ok_for_quad_peep (rtx reg1, rtx reg2)
*************** registers_ok_for_quad_peep (rtx reg1, rt
*** 8605,8610 ****
--- 8602,8612 ----
    /* We might have been passed a SUBREG.  */
    if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
      return 0;
+
+   /* We might have been passed a pseudo register.   */
+   if (!HARD_REGISTER_NUM_P (REGNO (reg1))
+       || !HARD_REGISTER_NUM_P (REGNO (reg2)))
+     return 0;

    return (REGNO (reg1) == REGNO (reg2) - 1);
  }
*************** registers_ok_for_quad_peep (rtx reg1, rt
*** 8614,8623 ****
     (addr2 == addr1 + 8).  */

  int
! addrs_ok_for_quad_peep (rtx addr1, rtx addr2)
  {
    unsigned int reg1;
    int offset1;

    /* Extract an offset (if used) from the first addr.  */
    if (GET_CODE (addr1) == PLUS)
--- 8616,8633 ----
     (addr2 == addr1 + 8).  */

  int
! mems_ok_for_quad_peep (rtx mem1, rtx mem2)
  {
+   rtx addr1, addr2;
    unsigned int reg1;
    int offset1;
+
+   /* The mems cannot be volatile.  */
+   if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
+     return 0;
+
+   addr1 = XEXP (mem1, 0);
+   addr2 = XEXP (mem2, 0);

    /* Extract an offset (if used) from the first addr.  */
    if (GET_CODE (addr1) == PLUS)
Index: rs6000-protos.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000-protos.h,v
retrieving revision 1.77
diff -p -c -3 -r1.77 rs6000-protos.h
*** rs6000-protos.h	20 Apr 2004 02:13:19 -0000	1.77
--- rs6000-protos.h	28 Apr 2004 15:15:30 -0000
*************** extern int includes_rshift_p (rtx, rtx);
*** 102,108 ****
  extern int includes_rldic_lshift_p (rtx, rtx);
  extern int includes_rldicr_lshift_p (rtx, rtx);
  extern int registers_ok_for_quad_peep (rtx, rtx);
! extern int addrs_ok_for_quad_peep (rtx, rtx);
  extern bool gpr_or_gpr_p (rtx, rtx);
  extern enum reg_class secondary_reload_class (enum reg_class,
  					      enum machine_mode, rtx);
--- 102,108 ----
  extern int includes_rldic_lshift_p (rtx, rtx);
  extern int includes_rldicr_lshift_p (rtx, rtx);
  extern int registers_ok_for_quad_peep (rtx, rtx);
! extern int mems_ok_for_quad_peep (rtx, rtx);
  extern bool gpr_or_gpr_p (rtx, rtx);
  extern enum reg_class secondary_reload_class (enum reg_class,
  					      enum machine_mode, rtx);
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.303
diff -p -c -3 -r1.303 rs6000.md
*** rs6000.md	20 Apr 2004 02:13:16 -0000	1.303
--- rs6000.md	28 Apr 2004 15:15:30 -0000
***************
*** 9608,9636 ****

;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.

! (define_peephole ! [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (match_operand:DF 1 "memory_operand" "")) ! (set (match_operand:DF 2 "gpc_reg_operand" "=f") (match_operand:DF 3 "memory_operand" ""))] "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS && registers_ok_for_quad_peep (operands[0], operands[2]) ! && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) ! && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" ! "lfq%U1%X1 %0,%1")

! (define_peephole [(set (match_operand:DF 0 "memory_operand" "") (match_operand:DF 1 "gpc_reg_operand" "f")) (set (match_operand:DF 2 "memory_operand" "") (match_operand:DF 3 "gpc_reg_operand" "f"))] "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS ! && registers_ok_for_quad_peep (operands[1], operands[3]) ! && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) ! && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" ! "stfq%U0%X0 %1,%0") ;; TLS support.

--- 9608,9655 ----

;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.

! (define_insn "*lfq_power2"
!   [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
! 	(match_operand:TF 1 "memory_operand" ""))]
!   "TARGET_POWER2
!    && TARGET_HARD_FLOAT && TARGET_FPRS"
!    "lfq%U1%X1 %0,%1")
!
! (define_peephole2
!   [(set (match_operand:DF 0 "gpc_reg_operand" "")
  	(match_operand:DF 1 "memory_operand" ""))
!    (set (match_operand:DF 2 "gpc_reg_operand" "")
  	(match_operand:DF 3 "memory_operand" ""))]
    "TARGET_POWER2
     && TARGET_HARD_FLOAT && TARGET_FPRS
     && registers_ok_for_quad_peep (operands[0], operands[2])
!    && mems_ok_for_quad_peep (operands[1], operands[3])"
!   [(set (match_dup 0)
!         (match_dup 1))]
!   "operands[1] = widen_memory_access (operands[1], TFmode, 0);
!    operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
!
! (define_insn "*stfq_power2"
!   [(set (match_operand:TF 0 "memory_operand" "")
! 	(match_operand:TF 1 "gpc_reg_operand" "f"))]
!   "TARGET_POWER2
!    && TARGET_HARD_FLOAT && TARGET_FPRS"
!   "stfq%U0%X0 %1,%0")
!

! (define_peephole2
    [(set (match_operand:DF 0 "memory_operand" "")
  	(match_operand:DF 1 "gpc_reg_operand" "f"))
     (set (match_operand:DF 2 "memory_operand" "")
  	(match_operand:DF 3 "gpc_reg_operand" "f"))]
    "TARGET_POWER2
     && TARGET_HARD_FLOAT && TARGET_FPRS
!    && registers_ok_for_quad_peep (operands[0], operands[2])
!    && mems_ok_for_quad_peep (operands[1], operands[3])"
!   [(set (match_dup 0)
! 	(match_dup 1))]
!   "operands[1] = widen_memory_access (operands[1], TFmode, 0);
!    operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
  
  ;; TLS support.

Follow-Ups:
- Re: [Patch] [PPC] Convert peephole to peephole2
  - From: David Edelsohn

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