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Re: ARM/iwmmxt sibling call fix


On Thu, Apr 22, 2004 at 06:51:47PM +0100, Paul Brook wrote:
> On Thursday 22 April 2004 18:42, Daniel Jacobowitz wrote:
> > On Thu, Apr 22, 2004 at 06:37:25PM +0100, Paul Brook wrote:
> > > > By the way, I believe that most of the TARGET_REALLY_IWMMXT code
> > > > related to preserving the stack pointer alignment ought to be
> > > > conditionalized on ARM_DOUBLEWORD_ALIGN instead.
> > >
> > > Yes, but only if we would otherwise have adjusted the stack by exactly 4
> > > bytes.
> >
> > You mean, if the difference between the TARGET_REALLY_IWMMXT case and
> > ARM_DOUBLEWORD_ALIGN case would be exactly 4 bytes?  It always is 4 or
> > 0; all iWMMXt mandates is doubleword alignment.
> 
> No, I mean when frame_size+current_function_outgoing_args == 0. If this is not 
> the case we already have sub sp, sp, #<size> so we get the alignment for 
> free.

Do you mean this bit of arm_expand_prologue?
  if (offsets->outgoing_args != offsets->saved_args + saved_regs)

In that case, I guess nothing is necessary for the AAPCS case after
all, and using a cycle to save an extra register to preserve the
alignment would just be a space optimization.  Does that make sense?

There's a more efficient way to handle this for iwmmxt.  Right
now if we needed to save r4, r5, and r6, and wr0, we'd generate:

	stmfd	sp!, {r4, r5, r6, r7}
	wstrd	wr0, [sp, #-8]!
	...
	wldrd	wr0, [sp], #8
	ldmia	sp!, {r4, r5, r6, r7}

If we're also saving some iWMMXt register, though, we can do this:

	stmfd	sp!, {r4, r5, r6}
	wstrd	wr0, [sp, #-12]!
	...
	wldrd	wr0, [sp], #12
	ldmib	sp!, {r4, r5, r6}

I'm going to stand by the patch I submitted, which is a correctness
fix, but it would be nice to do the above instead - it's two cycles
shorter.  It doesn't work if we're saving no iWMMXt registers, but I
am guessing that the code you've added to align the stack for AAPCS
will handle this transparently.  I'll give it a try sometime.

-- 
Daniel Jacobowitz
MontaVista Software                         Debian GNU/Linux Developer


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