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Re: MIPS SB-1 DFA scheduler patch
On Mon, 2004-04-19 at 23:51, cgd@broadcom.com wrote:
> At Tue, 20 Apr 2004 06:12:04 +0000 (UTC), "Jim Wilson" wrote:
> > + ;; cycle ifetch bubble. We assume all branches predicated not taken.
> I don't know if this assumption is reasonable, esp. when thinking
> about loops.
There was no actual thought here. I added the comment to document what
the code was doing, just to make it clear that the timing number used
was the not predicted taken number, in case this was the wrong number.
I could add a ??? comment saying that this number should be played with,
but I am not sure if it will make any difference. Mostly we schedule
within basic blocks in which case this number is irrelevant. When we do
schedule across basic blocks, I don't know if the code will do anything
sensible with a branch latency. I very seriously doubt that there is
any code that tries to fill loops with instructions to avoid branch
latency stalls. I suppose if we have a long latency operation started
before the branch if will count 2 cycles against their completion, but I
doubt the gcc scheduler will do much else with branch latencies, and it
isn't clear if this case will have any noticeable affect on real
applications. The only thing we can do is experiment and see what
happens.
If we had software pipelining, then this branch latency stuff would be
much more important.
--
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com