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Re: Avoiding MIPS mthi/mflo and mtlo/mfhi hazards
- From: cgd at broadcom dot com
- To: echristo at redhat dot com
- Cc: "Richard Sandiford" <rsandifo at redhat dot com>,gcc-patches at gcc dot gnu dot org
- Date: 19 Apr 2004 15:53:42 -0700
- Subject: Re: Avoiding MIPS mthi/mflo and mtlo/mfhi hazards
- References: <87k70e3oqx.fsf@redhat.com><1082412574.3349.20.camel@dzur.sfbay.redhat.com><mailpost.1082412626.6973@news-sj1-1>
At Mon, 19 Apr 2004 22:10:26 +0000 (UTC), "Eric Christopher" wrote:
> Yeah, this is fine with me. Why, of course, the hw vendors made this
> dependence... :)
It's in the MIPS architecture AFAIK since since r2000.
Given that AFAIK the processor can finish hi or lo indepdently, in
separate cycles, you only know that the op is completely done by
reading them out (or, reading out the half that you care about).
If you write one half before the op is done, what makes you think the
other half *should* be OK?
Sounds like pathological SW to me. 8-)
cgd