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[PATCH, committed] Add POWER5 machine description
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Thu, 25 Mar 2004 12:47:45 -0500
- Subject: [PATCH, committed] Add POWER5 machine description
I have added POWER5 scheduler description to mainline. The patch
also generalizes some of the earlier POWER4 functionality to test for new
variables instead of specifically testing for a POWER4 processor type.
The differences are below.
power4.md and power5.md could be merged together, but my tests
showed that the combined automata took much longer to generate than two
separate automata.
David
* config/rs6000/rs6000.c (rs6000_always_hint): New variable.
(rs6000_sched_groups): New variable.
(processor_target_table): Add power5.
(rs6000_override_options): Set rs6000_sched_insert_nops,
rs6000_sched_costly_dep and rs6000_sched_restricted_insns_priority
from rs6000_sched_groups.
(output_cbranch): Use rs6000_always_hint.
(rs6000_variable_issue): Use rs6000_sched_groups.
(rs6000_adjust_cost): Add CPU_POWER5.
(is_microcoded_insn): Use rs6000_sched_groups.
(is_dispatch_slot_restricted): Use rs6000_sched_groups.
Return 2 for POWER5 cracked instructions.
(is_cracked_insn): Use rs6000_sched_groups.
(is_branch_slot_insn): Use rs6000_sched_groups.
(rs6000_issue_rate): Add CPU_POWER5.
(rs6000_sched_finish): Use rs6000_sched_groups.
(rs6000_rtx_costs): Add PROCESSOR_POWER5.
* config/rs6000/rs6000.h (processor_type): Add PROCESSOR_POWER5.
(DEFAULT_SCHED_COSTLY_DEP): Delete.
(DEFAULT_RESTRICTED_INSNS_PRIORITY): Delete.
(DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME): Delete.
* config/rs6000/rs6000.md (define_attr "cpu"): Add power5.
* config/rs6000/power5.md: New file.
* doc/invoke.texi: Add power5 option.
Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.615
diff -c -p -r1.615 rs6000.c
*** rs6000.c 24 Mar 2004 00:13:24 -0000 1.615
--- rs6000.c 25 Mar 2004 17:37:53 -0000
*************** struct rs6000_cpu_select rs6000_select[3
*** 124,129 ****
--- 124,135 ----
{ (const char *)0, "-mtune=", 1, 0 },
};
+ /* Always emit branch hint bits. */
+ static GTY(()) bool rs6000_always_hint;
+
+ /* Schedule instructions for group formation. */
+ static GTY(()) bool rs6000_sched_groups;
+
/* Support adjust_priority scheduler hook
and -mprioritize-restricted-insns= option. */
const char *rs6000_sched_restricted_insns_priority_str;
*************** rs6000_override_options (const char *def
*** 714,719 ****
--- 720,727 ----
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
{"power4", PROCESSOR_POWER4,
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
+ {"power5", PROCESSOR_POWER5,
+ POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
{"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
{"powerpc64", PROCESSOR_POWERPC64,
POWERPC_BASE_MASK | MASK_POWERPC64},
*************** rs6000_override_options (const char *def
*** 914,919 ****
--- 922,932 ----
rs6000_long_double_type_size = 64;
}
+ rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
+ && rs6000_cpu != PROCESSOR_POWER5);
+ rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
+ || rs6000_cpu == PROCESSOR_POWER5);
+
/* Handle -m(no-)longcall option. This is a bit of a cheap hack,
using TARGET_OPTIONS to handle a toggle switch, but we're out of
bits in target_flags so TARGET_SWITCHES cannot be used.
*************** rs6000_override_options (const char *def
*** 942,954 ****
}
/* Handle -mprioritize-restricted-insns option. */
! rs6000_sched_restricted_insns_priority = DEFAULT_RESTRICTED_INSNS_PRIORITY;
if (rs6000_sched_restricted_insns_priority_str)
rs6000_sched_restricted_insns_priority =
atoi (rs6000_sched_restricted_insns_priority_str);
/* Handle -msched-costly-dep option. */
! rs6000_sched_costly_dep = DEFAULT_SCHED_COSTLY_DEP;
if (rs6000_sched_costly_dep_str)
{
if (! strcmp (rs6000_sched_costly_dep_str, "no"))
--- 955,969 ----
}
/* Handle -mprioritize-restricted-insns option. */
! rs6000_sched_restricted_insns_priority
! = (rs6000_sched_groups ? 1 : 0);
if (rs6000_sched_restricted_insns_priority_str)
rs6000_sched_restricted_insns_priority =
atoi (rs6000_sched_restricted_insns_priority_str);
/* Handle -msched-costly-dep option. */
! rs6000_sched_costly_dep
! = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
if (rs6000_sched_costly_dep_str)
{
if (! strcmp (rs6000_sched_costly_dep_str, "no"))
*************** rs6000_override_options (const char *def
*** 964,970 ****
}
/* Handle -minsert-sched-nops option. */
! rs6000_sched_insert_nops = DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME;
if (rs6000_sched_insert_nops_str)
{
if (! strcmp (rs6000_sched_insert_nops_str, "no"))
--- 979,986 ----
}
/* Handle -minsert-sched-nops option. */
! rs6000_sched_insert_nops
! = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
if (rs6000_sched_insert_nops_str)
{
if (! strcmp (rs6000_sched_insert_nops_str, "no"))
*************** output_cbranch (rtx op, const char *labe
*** 10066,10072 ****
{
/* PROB is the difference from 50%. */
int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
- bool always_hint = rs6000_cpu != PROCESSOR_POWER4;
/* Only hint for highly probable/improbable branches on newer
cpus as static prediction overrides processor dynamic
--- 10082,10087 ----
*************** output_cbranch (rtx op, const char *labe
*** 10074,10080 ****
assume not taken for branches that are very close to 50% as a
mispredicted taken branch is more expensive than a
mispredicted not-taken branch. */
! if (always_hint
|| abs (prob) > REG_BR_PROB_BASE / 100 * 48)
{
if (abs (prob) > REG_BR_PROB_BASE / 20
--- 10089,10095 ----
assume not taken for branches that are very close to 50% as a
mispredicted taken branch is more expensive than a
mispredicted not-taken branch. */
! if (rs6000_always_hint
|| abs (prob) > REG_BR_PROB_BASE / 100 * 48)
{
if (abs (prob) > REG_BR_PROB_BASE / 20
*************** rs6000_variable_issue (FILE *stream ATTR
*** 13885,13891 ****
|| GET_CODE (PATTERN (insn)) == CLOBBER)
return more;
! if (rs6000_cpu == PROCESSOR_POWER4)
{
if (is_microcoded_insn (insn))
return 0;
--- 13900,13906 ----
|| GET_CODE (PATTERN (insn)) == CLOBBER)
return more;
! if (rs6000_sched_groups)
{
if (is_microcoded_insn (insn))
return 0;
*************** rs6000_adjust_cost (rtx insn, rtx link,
*** 13933,13939 ****
|| rs6000_cpu_attr == CPU_PPC750
|| rs6000_cpu_attr == CPU_PPC7400
|| rs6000_cpu_attr == CPU_PPC7450
! || rs6000_cpu_attr == CPU_POWER4)
&& recog_memoized (dep_insn)
&& (INSN_CODE (dep_insn) >= 0)
&& (get_attr_type (dep_insn) == TYPE_CMP
--- 13948,13955 ----
|| rs6000_cpu_attr == CPU_PPC750
|| rs6000_cpu_attr == CPU_PPC7400
|| rs6000_cpu_attr == CPU_PPC7450
! || rs6000_cpu_attr == CPU_POWER4
! || rs6000_cpu_attr == CPU_POWER5)
&& recog_memoized (dep_insn)
&& (INSN_CODE (dep_insn) >= 0)
&& (get_attr_type (dep_insn) == TYPE_CMP
*************** is_microcoded_insn (rtx insn)
*** 13965,13971 ****
|| GET_CODE (PATTERN (insn)) == CLOBBER)
return false;
! if (rs6000_cpu == PROCESSOR_POWER4)
{
enum attr_type type = get_attr_type (insn);
if (type == TYPE_LOAD_EXT_U
--- 13981,13987 ----
|| GET_CODE (PATTERN (insn)) == CLOBBER)
return false;
! if (rs6000_sched_groups)
{
enum attr_type type = get_attr_type (insn);
if (type == TYPE_LOAD_EXT_U
*************** is_dispatch_slot_restricted (rtx insn)
*** 13990,13996 ****
{
enum attr_type type;
! if (rs6000_cpu != PROCESSOR_POWER4)
return 0;
if (!insn
--- 14006,14012 ----
{
enum attr_type type;
! if (!rs6000_sched_groups)
return 0;
if (!insn
*************** is_dispatch_slot_restricted (rtx insn)
*** 14002,14022 ****
type = get_attr_type (insn);
! switch (type){
! case TYPE_MFCR:
! case TYPE_MFCRF:
! case TYPE_MTCR:
! case TYPE_DELAYED_CR:
! case TYPE_CR_LOGICAL:
! case TYPE_MTJMPR:
! case TYPE_MFJMPR:
! return 1;
! case TYPE_IDIV:
! case TYPE_LDIV:
! return 2;
! default:
! return 0;
! }
}
/* The function returns true if INSN is cracked into 2 instructions
--- 14018,14042 ----
type = get_attr_type (insn);
! switch (type)
! {
! case TYPE_MFCR:
! case TYPE_MFCRF:
! case TYPE_MTCR:
! case TYPE_DELAYED_CR:
! case TYPE_CR_LOGICAL:
! case TYPE_MTJMPR:
! case TYPE_MFJMPR:
! return 1;
! case TYPE_IDIV:
! case TYPE_LDIV:
! return 2;
! default:
! if (rs6000_cpu == PROCESSOR_POWER5
! && is_cracked_insn (insn))
! return 2;
! return 0;
! }
}
/* The function returns true if INSN is cracked into 2 instructions
*************** is_cracked_insn (rtx insn)
*** 14030,14036 ****
|| GET_CODE (PATTERN (insn)) == CLOBBER)
return false;
! if (rs6000_cpu == PROCESSOR_POWER4)
{
enum attr_type type = get_attr_type (insn);
if (type == TYPE_LOAD_U || type == TYPE_STORE_U
--- 14050,14056 ----
|| GET_CODE (PATTERN (insn)) == CLOBBER)
return false;
! if (rs6000_sched_groups)
{
enum attr_type type = get_attr_type (insn);
if (type == TYPE_LOAD_U || type == TYPE_STORE_U
*************** is_branch_slot_insn (rtx insn)
*** 14058,14064 ****
|| GET_CODE (PATTERN (insn)) == CLOBBER)
return false;
! if (rs6000_cpu == PROCESSOR_POWER4)
{
enum attr_type type = get_attr_type (insn);
if (type == TYPE_BRANCH || type == TYPE_JMPREG)
--- 14078,14084 ----
|| GET_CODE (PATTERN (insn)) == CLOBBER)
return false;
! if (rs6000_sched_groups)
{
enum attr_type type = get_attr_type (insn);
if (type == TYPE_BRANCH || type == TYPE_JMPREG)
*************** rs6000_issue_rate (void)
*** 14158,14163 ****
--- 14178,14184 ----
case CPU_PPC630:
return 4;
case CPU_POWER4:
+ case CPU_POWER5:
return 5;
default:
return 1;
*************** rs6000_sched_finish (FILE *dump, int sch
*** 14711,14717 ****
if (sched_verbose)
fprintf (dump, "=== Finishing schedule.\n");
! if (reload_completed && rs6000_cpu == PROCESSOR_POWER4)
{
if (rs6000_sched_insert_nops == sched_finish_none)
return;
--- 14732,14738 ----
if (sched_verbose)
fprintf (dump, "=== Finishing schedule.\n");
! if (reload_completed && rs6000_sched_groups)
{
if (rs6000_sched_insert_nops == sched_finish_none)
return;
*************** rs6000_rtx_costs (rtx x, int code, int o
*** 15905,15910 ****
--- 15926,15932 ----
return true;
case PROCESSOR_POWER4:
+ case PROCESSOR_POWER5:
*total = (GET_CODE (XEXP (x, 1)) != CONST_INT
? GET_MODE (XEXP (x, 1)) != DImode
? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)
*************** rs6000_rtx_costs (rtx x, int code, int o
*** 15990,15995 ****
--- 16012,16018 ----
return true;
case PROCESSOR_POWER4:
+ case PROCESSOR_POWER5:
*total = (GET_MODE (XEXP (x, 1)) != DImode
? COSTS_N_INSNS (18)
: COSTS_N_INSNS (34));
Index: rs6000.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.318
diff -c -p -r1.318 rs6000.h
*** rs6000.h 18 Mar 2004 16:39:44 -0000 1.318
--- rs6000.h 25 Mar 2004 17:37:53 -0000
*************** enum processor_type
*** 386,392 ****
PROCESSOR_PPC7400,
PROCESSOR_PPC7450,
PROCESSOR_PPC8540,
! PROCESSOR_POWER4
};
extern enum processor_type rs6000_cpu;
--- 386,393 ----
PROCESSOR_PPC7400,
PROCESSOR_PPC7450,
PROCESSOR_PPC8540,
! PROCESSOR_POWER4,
! PROCESSOR_POWER5
};
extern enum processor_type rs6000_cpu;
*************** extern const char *rs6000_warn_altivec_l
*** 549,567 ****
#else
#define TARGET_ALIGN_NATURAL 0
#endif
-
- /* Set a default value for DEFAULT_SCHED_COSTLY_DEP used by target hook
- is_costly_dependence. */
- #define DEFAULT_SCHED_COSTLY_DEP \
- (rs6000_cpu == PROCESSOR_POWER4 ? store_to_load_dep_costly : no_dep_costly)
-
- /* Define if the target has restricted dispatch slot instructions. */
- #define DEFAULT_RESTRICTED_INSNS_PRIORITY (rs6000_cpu == PROCESSOR_POWER4 ? 1 : 0)
-
- /* Set a default value for post scheduling nop insertion scheme
- (used by taget hook sched_finish). */
- #define DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME \
- (rs6000_cpu == PROCESSOR_POWER4 ? sched_finish_regroup_exact : sched_finish_none)
#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
--- 550,555 ----
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.299
diff -c -p -r1.299 rs6000.md
*** rs6000.md 9 Mar 2004 12:10:25 -0000 1.299
--- rs6000.md 25 Mar 2004 17:37:54 -0000
***************
*** 82,88 ****
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.
! (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4"
(const (symbol_ref "rs6000_cpu_attr")))
(automata_option "ndfa")
--- 82,88 ----
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.
! (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
(const (symbol_ref "rs6000_cpu_attr")))
(automata_option "ndfa")
***************
*** 99,104 ****
--- 99,105 ----
(include "7450.md")
(include "8540.md")
(include "power4.md")
+ (include "power5.md")
;; Start with fixed-point load and store insns. Here we put only the more