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PATCH: PR 14702


This patch fixes constraints in mmx_pshufw, sse2_pshufd, sse2_pshuflw,
sse2_pshufhw (PR 14702).

2004-03-24  Serge Belyshev  <1319@bot.ru>

	PR target/14702
	* config/i386/i386.md: fix source operand constraints in
	mmx_pshufw, sse2_pshufd, sse2_pshuflw, sse2_pshufhw

Index: config/i386/i386.md
===================================================================
RCS file: /cvsroot/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.520
diff -c -3 -p -r1.520 i386.md
*** config/i386/i386.md	16 Mar 2004 23:29:22 -0000	1.520
--- config/i386/i386.md	24 Mar 2004 02:27:59 -0000
***************
*** 20576,20582 ****
  
  (define_insn "mmx_pshufw"
    [(set (match_operand:V4HI 0 "register_operand" "=y")
!         (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
  		      (match_operand:SI 2 "immediate_operand" "i")]
  		     UNSPEC_SHUFFLE))]
    "TARGET_SSE || TARGET_3DNOW_A"
--- 20576,20582 ----
  
  (define_insn "mmx_pshufw"
    [(set (match_operand:V4HI 0 "register_operand" "=y")
!         (unspec:V4HI [(match_operand:V4HI 1 "nonimmediate_operand" "ym")
  		      (match_operand:SI 2 "immediate_operand" "i")]
  		     UNSPEC_SHUFFLE))]
    "TARGET_SSE || TARGET_3DNOW_A"
***************
*** 22273,22279 ****
  
  (define_insn "sse2_pshufd"
    [(set (match_operand:V4SI 0 "register_operand" "=x")
!         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
  		      (match_operand:SI 2 "immediate_operand" "i")]
  		     UNSPEC_SHUFFLE))]
    "TARGET_SSE2"
--- 22273,22279 ----
  
  (define_insn "sse2_pshufd"
    [(set (match_operand:V4SI 0 "register_operand" "=x")
!         (unspec:V4SI [(match_operand:V4SI 1 "nonimmediate_operand" "xm")
  		      (match_operand:SI 2 "immediate_operand" "i")]
  		     UNSPEC_SHUFFLE))]
    "TARGET_SSE2"
***************
*** 22283,22289 ****
  
  (define_insn "sse2_pshuflw"
    [(set (match_operand:V8HI 0 "register_operand" "=x")
!         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
  		      (match_operand:SI 2 "immediate_operand" "i")]
  		     UNSPEC_PSHUFLW))]
    "TARGET_SSE2"
--- 22283,22289 ----
  
  (define_insn "sse2_pshuflw"
    [(set (match_operand:V8HI 0 "register_operand" "=x")
!         (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")
  		      (match_operand:SI 2 "immediate_operand" "i")]
  		     UNSPEC_PSHUFLW))]
    "TARGET_SSE2"
***************
*** 22293,22299 ****
  
  (define_insn "sse2_pshufhw"
    [(set (match_operand:V8HI 0 "register_operand" "=x")
!         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
  		      (match_operand:SI 2 "immediate_operand" "i")]
  		     UNSPEC_PSHUFHW))]
    "TARGET_SSE2"
--- 22293,22299 ----
  
  (define_insn "sse2_pshufhw"
    [(set (match_operand:V8HI 0 "register_operand" "=x")
!         (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")
  		      (match_operand:SI 2 "immediate_operand" "i")]
  		     UNSPEC_PSHUFHW))]
    "TARGET_SSE2"


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