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new mips type attributes: fpload, fpidxload, fpstore, fpidxstore
- From: Jim Wilson <wilson at specifixinc dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: 11 Mar 2004 21:28:01 -0800
- Subject: new mips type attributes: fpload, fpidxload, fpstore, fpidxstore
This is the first patch for expanding the type attributes for the SB-1 DFA
scheduler. I am submitting multiple patches so that they will be easier to
review.
When developing this, I initially renamed load to old_load and store to
old_store, to ensure that I caught every current use that needed to be fixed.
Then I changed them back after I was done converting the types.
The sr71k.md file has separate load/store and fload/fstore patterns that check
the mode of the operand. This isn't quite correct, as integer modes could be
used for FP loads/stores, and vice versa. I deleted the mode checks, and
used the new fp load/store types in the fload/fstore patterns. This is a
behaviour change, but should result in better scheduled code.
The 5400.md file has buggy load/store patterns. There is a load pattern that
rejects FP modes as above. However, there is no load pattern that matches
FP modes, so FP loads are currently scheduled wrong. I don't have a 5400
manual handy, so I just deleted the mode checks, on the assumption that fp
loads should be handled the same as integer loads. There are two store
patterns, one for integer stores and one for FP stores, but they are otherwise
identical so they could be combined into one pattern. I did not change this.
This was tested with a mips-elf cross compiler build, and make -k check in the
gcc directory.
Comments?
2004-03-11 James E Wilson <wilson@specifixinc.com>
* config/mips/mips.md (type): Split load into load, fpload, fpidxload.
Split store into store, fpstore, fpidxstore. Fix all uses.
* config/mips/5400.md (ir_vr54_load, ir_vr54_store, ir_vr54_fstore):
Likewise.
* config/mips/5500.md (ir_vr55_load, i5_vr55_store): Likewise.
* config/mips/7000.md (rm7_ld, rm7_st): Likewise.
* config/mips/9000.md (rm9k_load, rm9k_store): Likewise.
* config/mips/sr71k.md (ir_sr70_load, ir_sr70_store, ir_sr70_fload,
ir_sr70_fstore): Likewise.
Index: 5400.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/5400.md,v
retrieving revision 1.3
diff -p -r1.3 5400.md
*** 5400.md 15 Jul 2003 08:16:44 -0000 1.3
--- 5400.md 12 Mar 2004 03:07:38 -0000
***************
*** 26,45 ****
(define_insn_reservation "ir_vr54_load" 2
(and (eq_attr "cpu" "r5400")
! (and (eq_attr "type" "load")
! (eq_attr "mode" "!SF,DF,FPSW")))
"vr54_mem")
(define_insn_reservation "ir_vr54_store" 1
(and (eq_attr "cpu" "r5400")
! (and (eq_attr "type" "store")
! (eq_attr "mode" "!SF,DF,FPSW")))
"vr54_mem")
(define_insn_reservation "ir_vr54_fstore" 1
(and (eq_attr "cpu" "r5400")
! (and (eq_attr "type" "store")
! (eq_attr "mode" "SF,DF")))
"vr54_mem")
--- 26,42 ----
(define_insn_reservation "ir_vr54_load" 2
(and (eq_attr "cpu" "r5400")
! (eq_attr "type" "load,fpload,fpidxload"))
"vr54_mem")
(define_insn_reservation "ir_vr54_store" 1
(and (eq_attr "cpu" "r5400")
! (eq_attr "type" "store"))
"vr54_mem")
(define_insn_reservation "ir_vr54_fstore" 1
(and (eq_attr "cpu" "r5400")
! (eq_attr "type" "fpstore,fpidxstore"))
"vr54_mem")
Index: 5500.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/5500.md,v
retrieving revision 1.3
diff -p -r1.3 5500.md
*** 5500.md 15 Jul 2003 08:16:44 -0000 1.3
--- 5500.md 12 Mar 2004 03:07:39 -0000
***************
*** 28,39 ****
(define_insn_reservation "ir_vr55_load" 3
(and (eq_attr "cpu" "r5500")
! (eq_attr "type" "load"))
"vr55_mem")
(define_insn_reservation "ir_vr55_store" 1
(and (eq_attr "cpu" "r5500")
! (eq_attr "type" "store"))
"vr55_mem")
;; This reservation is for conditional move based on integer
--- 28,39 ----
(define_insn_reservation "ir_vr55_load" 3
(and (eq_attr "cpu" "r5500")
! (eq_attr "type" "load,fpload,fpidxload"))
"vr55_mem")
(define_insn_reservation "ir_vr55_store" 1
(and (eq_attr "cpu" "r5500")
! (eq_attr "type" "store,fpstore,fpidxstore"))
"vr55_mem")
;; This reservation is for conditional move based on integer
Index: 7000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/7000.md,v
retrieving revision 1.1
diff -p -r1.1 7000.md
*** 7000.md 15 Jul 2003 08:34:54 -0000 1.1
--- 7000.md 12 Mar 2004 03:07:39 -0000
***************
*** 92,102 ****
"rm7_iaddsub")
(define_insn_reservation "rm7_ld" 2 (and (eq_attr "cpu" "r7000")
! (eq_attr "type" "load"))
"rm7_imem")
(define_insn_reservation "rm7_st" 1 (and (eq_attr "cpu" "r7000")
! (eq_attr "type" "store"))
"rm7_imem")
(define_insn_reservation "rm7_idiv_si" 36 (and (eq_attr "cpu" "r7000")
--- 92,102 ----
"rm7_iaddsub")
(define_insn_reservation "rm7_ld" 2 (and (eq_attr "cpu" "r7000")
! (eq_attr "type" "load,fpload,fpidxload"))
"rm7_imem")
(define_insn_reservation "rm7_st" 1 (and (eq_attr "cpu" "r7000")
! (eq_attr "type" "store,fpstore,fpidxstore"))
"rm7_imem")
(define_insn_reservation "rm7_idiv_si" 36 (and (eq_attr "cpu" "r7000")
Index: 9000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/9000.md,v
retrieving revision 1.1
diff -p -r1.1 9000.md
*** 9000.md 15 Jul 2003 08:44:26 -0000 1.1
--- 9000.md 12 Mar 2004 03:07:39 -0000
***************
*** 42,53 ****
(define_insn_reservation "rm9k_load" 3
(and (eq_attr "cpu" "r9000")
! (eq_attr "type" "load"))
"rm9k_m")
(define_insn_reservation "rm9k_store" 1
(and (eq_attr "cpu" "r9000")
! (eq_attr "type" "store"))
"rm9k_m")
(define_insn_reservation "rm9k_int" 1
--- 42,53 ----
(define_insn_reservation "rm9k_load" 3
(and (eq_attr "cpu" "r9000")
! (eq_attr "type" "load,fpload,fpidxload"))
"rm9k_m")
(define_insn_reservation "rm9k_store" 1
(and (eq_attr "cpu" "r9000")
! (eq_attr "type" "store,fpstore,fpidxstore"))
"rm9k_m")
(define_insn_reservation "rm9k_int" 1
Index: mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.222
diff -p -r1.222 mips.md
*** mips.md 1 Mar 2004 19:40:10 -0000 1.222
--- mips.md 12 Mar 2004 03:07:50 -0000
***************
*** 93,99 ****
--- 93,103 ----
;; jump unconditional jump
;; call unconditional call
;; load load instruction(s)
+ ;; fpload floating point load
+ ;; fpidxload floating point indexed load
;; store store instruction(s)
+ ;; fpstore floating point store
+ ;; fpidxstore floating point indexed store
;; prefetch memory prefetch (register + offset)
;; prefetchx memory indexed prefetch (register + register)
;; move data movement within same register set
***************
*** 120,126 ****
;; multi multiword sequence (or user asm statements)
;; nop no operation
(define_attr "type"
! "unknown,branch,jump,call,load,store,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
(cond [(eq_attr "jal" "!unset") (const_string "call")
(eq_attr "got" "load") (const_string "load")]
(const_string "unknown")))
--- 124,130 ----
;; multi multiword sequence (or user asm statements)
;; nop no operation
(define_attr "type"
! "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
(cond [(eq_attr "jal" "!unset") (const_string "call")
(eq_attr "got" "load") (const_string "load")]
(const_string "unknown")))
***************
*** 182,190 ****
(eq_attr "type" "const")
(symbol_ref "mips_const_insns (operands[1]) * 4")
! (eq_attr "type" "load")
(symbol_ref "mips_fetch_insns (operands[1]) * 4")
! (eq_attr "type" "store")
(symbol_ref "mips_fetch_insns (operands[0]) * 4")
;; In the worst case, a call macro will take 8 instructions:
--- 186,194 ----
(eq_attr "type" "const")
(symbol_ref "mips_const_insns (operands[1]) * 4")
! (eq_attr "type" "load,fpload,fpidxload")
(symbol_ref "mips_fetch_insns (operands[1]) * 4")
! (eq_attr "type" "store,fpstore,fpidxstore")
(symbol_ref "mips_fetch_insns (operands[0]) * 4")
;; In the worst case, a call macro will take 8 instructions:
***************
*** 219,225 ****
;; of this one. HILO means that the next two instructions cannot
;; write to HI or LO.
(define_attr "hazard" "none,delay,hilo"
! (cond [(and (eq_attr "type" "load")
(ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
(const_string "delay")
--- 223,229 ----
;; of this one. HILO means that the next two instructions cannot
;; write to HI or LO.
(define_attr "hazard" "none,delay,hilo"
! (cond [(and (eq_attr "type" "load,fpload,fpidxload")
(ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
(const_string "delay")
***************
*** 301,316 ****
;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
(define_function_unit "memory" 1 0
! (and (eq_attr "type" "load")
(eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
3 0)
(define_function_unit "memory" 1 0
! (and (eq_attr "type" "load")
(eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
2 0)
! (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
(define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
--- 305,322 ----
;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
(define_function_unit "memory" 1 0
! (and (eq_attr "type" "load,fpload,fpidxload")
(eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
3 0)
(define_function_unit "memory" 1 0
! (and (eq_attr "type" "load,fpload,fpidxload")
(eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
2 0)
! (define_function_unit "memory" 1 0
! (eq_attr "type" "store,fpstore,fpidxstore")
! 1 0)
(define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
*************** dsrl\t%3,%3,1\n\
*** 4551,4557 ****
|| (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
|| operands[1] == CONST0_RTX (DImode))"
{ return mips_output_move (operands[0], operands[1]); }
! [(set_attr "type" "move,const,const,load,store,move,xfer,load,xfer,store,hilo,hilo,hilo,xfer,load,xfer,store")
(set_attr "mode" "DI")
(set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,8,*,8,*")])
--- 4557,4563 ----
|| (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
|| operands[1] == CONST0_RTX (DImode))"
{ return mips_output_move (operands[0], operands[1]); }
! [(set_attr "type" "move,const,const,load,store,move,xfer,fpload,xfer,fpstore,hilo,hilo,hilo,xfer,load,xfer,store")
(set_attr "mode" "DI")
(set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,8,*,8,*")])
*************** dsrl\t%3,%3,1\n\
*** 4676,4682 ****
|| register_operand (operands[1], SImode)
|| (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
{ return mips_output_move (operands[0], operands[1]); }
! [(set_attr "type" "move,const,const,load,store,move,xfer,load,xfer,store,xfer,xfer,hilo,hilo,hilo,xfer,load,xfer,store")
(set_attr "mode" "SI")
(set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,4,*,4,*")])
--- 4682,4688 ----
|| register_operand (operands[1], SImode)
|| (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
{ return mips_output_move (operands[0], operands[1]); }
! [(set_attr "type" "move,const,const,load,store,move,xfer,fpload,xfer,fpstore,xfer,xfer,hilo,hilo,hilo,xfer,load,xfer,store")
(set_attr "mode" "SI")
(set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,4,*,4,*")])
*************** dsrl\t%3,%3,1\n\
*** 4794,4800 ****
(match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
"ISA_HAS_8CC && TARGET_HARD_FLOAT"
{ return mips_output_move (operands[0], operands[1]); }
! [(set_attr "type" "move,move,load,store,xfer,xfer,move,load,store")
(set_attr "mode" "SI")
(set_attr "length" "8,4,*,*,4,4,4,*,*")])
--- 4800,4806 ----
(match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
"ISA_HAS_8CC && TARGET_HARD_FLOAT"
{ return mips_output_move (operands[0], operands[1]); }
! [(set_attr "type" "move,move,load,store,xfer,xfer,move,fpload,fpstore")
(set_attr "mode" "SI")
(set_attr "length" "8,4,*,*,4,4,4,*,*")])
*************** dsrl\t%3,%3,1\n\
*** 4851,4857 ****
(match_operand:SI 2 "register_operand" "d"))))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"lwxc1\t%0,%1(%2)"
! [(set_attr "type" "load")
(set_attr "mode" "SF")
(set_attr "length" "4")])
--- 4857,4863 ----
(match_operand:SI 2 "register_operand" "d"))))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"lwxc1\t%0,%1(%2)"
! [(set_attr "type" "fpidxload")
(set_attr "mode" "SF")
(set_attr "length" "4")])
*************** dsrl\t%3,%3,1\n\
*** 4861,4867 ****
(match_operand:DI 2 "register_operand" "d"))))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"lwxc1\t%0,%1(%2)"
! [(set_attr "type" "load")
(set_attr "mode" "SF")
(set_attr "length" "4")])
--- 4867,4873 ----
(match_operand:DI 2 "register_operand" "d"))))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"lwxc1\t%0,%1(%2)"
! [(set_attr "type" "fpidxload")
(set_attr "mode" "SF")
(set_attr "length" "4")])
*************** dsrl\t%3,%3,1\n\
*** 4871,4877 ****
(match_operand:SI 2 "register_operand" "d"))))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ldxc1\t%0,%1(%2)"
! [(set_attr "type" "load")
(set_attr "mode" "DF")
(set_attr "length" "4")])
--- 4877,4883 ----
(match_operand:SI 2 "register_operand" "d"))))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ldxc1\t%0,%1(%2)"
! [(set_attr "type" "fpidxload")
(set_attr "mode" "DF")
(set_attr "length" "4")])
*************** dsrl\t%3,%3,1\n\
*** 4881,4887 ****
(match_operand:DI 2 "register_operand" "d"))))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ldxc1\t%0,%1(%2)"
! [(set_attr "type" "load")
(set_attr "mode" "DF")
(set_attr "length" "4")])
--- 4887,4893 ----
(match_operand:DI 2 "register_operand" "d"))))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ldxc1\t%0,%1(%2)"
! [(set_attr "type" "fpidxload")
(set_attr "mode" "DF")
(set_attr "length" "4")])
*************** dsrl\t%3,%3,1\n\
*** 4891,4897 ****
(match_operand:SF 0 "register_operand" "f"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"swxc1\t%0,%1(%2)"
! [(set_attr "type" "store")
(set_attr "mode" "SF")
(set_attr "length" "4")])
--- 4897,4903 ----
(match_operand:SF 0 "register_operand" "f"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"swxc1\t%0,%1(%2)"
! [(set_attr "type" "fpidxstore")
(set_attr "mode" "SF")
(set_attr "length" "4")])
*************** dsrl\t%3,%3,1\n\
*** 4901,4907 ****
(match_operand:SF 0 "register_operand" "f"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"swxc1\t%0,%1(%2)"
! [(set_attr "type" "store")
(set_attr "mode" "SF")
(set_attr "length" "4")])
--- 4907,4913 ----
(match_operand:SF 0 "register_operand" "f"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"swxc1\t%0,%1(%2)"
! [(set_attr "type" "fpidxstore")
(set_attr "mode" "SF")
(set_attr "length" "4")])
*************** dsrl\t%3,%3,1\n\
*** 4911,4917 ****
(match_operand:DF 0 "register_operand" "f"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sdxc1\t%0,%1(%2)"
! [(set_attr "type" "store")
(set_attr "mode" "DF")
(set_attr "length" "4")])
--- 4917,4923 ----
(match_operand:DF 0 "register_operand" "f"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sdxc1\t%0,%1(%2)"
! [(set_attr "type" "fpidxstore")
(set_attr "mode" "DF")
(set_attr "length" "4")])
*************** dsrl\t%3,%3,1\n\
*** 4921,4927 ****
(match_operand:DF 0 "register_operand" "f"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sdxc1\t%0,%1(%2)"
! [(set_attr "type" "store")
(set_attr "mode" "DF")
(set_attr "length" "4")])
--- 4927,4933 ----
(match_operand:DF 0 "register_operand" "f"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sdxc1\t%0,%1(%2)"
! [(set_attr "type" "fpidxstore")
(set_attr "mode" "DF")
(set_attr "length" "4")])
*************** dsrl\t%3,%3,1\n\
*** 5160,5166 ****
&& (register_operand (operands[0], SFmode)
|| nonmemory_operand (operands[1], SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
! [(set_attr "type" "move,xfer,load,store,xfer,xfer,move,load,store")
(set_attr "mode" "SF")
(set_attr "length" "4,4,*,*,4,4,4,*,*")])
--- 5166,5172 ----
&& (register_operand (operands[0], SFmode)
|| nonmemory_operand (operands[1], SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
! [(set_attr "type" "move,xfer,fpload,fpstore,xfer,xfer,move,load,store")
(set_attr "mode" "SF")
(set_attr "length" "4,4,*,*,4,4,4,*,*")])
*************** dsrl\t%3,%3,1\n\
*** 5207,5213 ****
&& (register_operand (operands[0], DFmode)
|| nonmemory_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
! [(set_attr "type" "move,xfer,load,store,xfer,xfer,move,load,store")
(set_attr "mode" "DF")
(set_attr "length" "4,4,*,*,4,4,4,*,*")])
--- 5213,5219 ----
&& (register_operand (operands[0], DFmode)
|| nonmemory_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
! [(set_attr "type" "move,xfer,fpload,fpstore,xfer,xfer,move,load,store")
(set_attr "mode" "DF")
(set_attr "length" "4,4,*,*,4,4,4,*,*")])
*************** dsrl\t%3,%3,1\n\
*** 5218,5224 ****
&& (register_operand (operands[0], DFmode)
|| nonmemory_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
! [(set_attr "type" "move,xfer,load,store,xfer,xfer,move,load,store")
(set_attr "mode" "DF")
(set_attr "length" "4,8,*,*,8,8,8,*,*")])
--- 5224,5230 ----
&& (register_operand (operands[0], DFmode)
|| nonmemory_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
! [(set_attr "type" "move,xfer,fpload,fpstore,xfer,xfer,move,load,store")
(set_attr "mode" "DF")
(set_attr "length" "4,8,*,*,8,8,8,*,*")])
*************** dsrl\t%3,%3,1\n\
*** 5280,5286 ****
operands[0] = mips_subword (operands[0], 0);
return mips_output_move (operands[0], operands[1]);
}
! [(set_attr "type" "xfer,load")
(set_attr "mode" "SF")
(set_attr "length" "4")])
--- 5286,5292 ----
operands[0] = mips_subword (operands[0], 0);
return mips_output_move (operands[0], operands[1]);
}
! [(set_attr "type" "xfer,fpload")
(set_attr "mode" "SF")
(set_attr "length" "4")])
*************** dsrl\t%3,%3,1\n\
*** 5296,5302 ****
operands[0] = mips_subword (operands[0], 1);
return mips_output_move (operands[0], operands[1]);
}
! [(set_attr "type" "xfer,load")
(set_attr "mode" "SF")
(set_attr "length" "4")])
--- 5302,5308 ----
operands[0] = mips_subword (operands[0], 1);
return mips_output_move (operands[0], operands[1]);
}
! [(set_attr "type" "xfer,fpload")
(set_attr "mode" "SF")
(set_attr "length" "4")])
*************** dsrl\t%3,%3,1\n\
*** 5311,5317 ****
operands[1] = mips_subword (operands[1], 1);
return mips_output_move (operands[0], operands[1]);
}
! [(set_attr "type" "xfer,store")
(set_attr "mode" "SF")
(set_attr "length" "4")])
--- 5317,5323 ----
operands[1] = mips_subword (operands[1], 1);
return mips_output_move (operands[0], operands[1]);
}
! [(set_attr "type" "xfer,fpstore")
(set_attr "mode" "SF")
(set_attr "length" "4")])
Index: sr71k.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/sr71k.md,v
retrieving revision 1.5
diff -p -r1.5 sr71k.md
*** sr71k.md 15 Jul 2003 08:16:44 -0000 1.5
--- sr71k.md 12 Mar 2004 03:07:50 -0000
***************
*** 141,155 ****
(define_insn_reservation "ir_sr70_load"
2
(and (eq_attr "cpu" "sr71000")
! (and (eq_attr "type" "load")
! (eq_attr "mode" "!SF,DF,FPSW")))
"ri_mem")
(define_insn_reservation "ir_sr70_store"
1
(and (eq_attr "cpu" "sr71000")
! (and (eq_attr "type" "store")
! (eq_attr "mode" "!SF,DF,FPSW")))
"ri_mem")
--- 141,153 ----
(define_insn_reservation "ir_sr70_load"
2
(and (eq_attr "cpu" "sr71000")
! (eq_attr "type" "load"))
"ri_mem")
(define_insn_reservation "ir_sr70_store"
1
(and (eq_attr "cpu" "sr71000")
! (eq_attr "type" "store"))
"ri_mem")
***************
*** 159,173 ****
(define_insn_reservation "ir_sr70_fload"
9
(and (eq_attr "cpu" "sr71000")
! (and (eq_attr "type" "load")
! (eq_attr "mode" "SF,DF")))
"(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
(define_insn_reservation "ir_sr70_fstore"
1
(and (eq_attr "cpu" "sr71000")
! (and (eq_attr "type" "store")
! (eq_attr "mode" "SF,DF")))
"(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
--- 157,169 ----
(define_insn_reservation "ir_sr70_fload"
9
(and (eq_attr "cpu" "sr71000")
! (eq_attr "type" "fpload,fpidxload"))
"(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
(define_insn_reservation "ir_sr70_fstore"
1
(and (eq_attr "cpu" "sr71000")
! (eq_attr "type" "fpstore,fpidxstore"))
"(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
--
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com