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[PATCH]: Disable -fweb on 68hc11


The web optimisation breaks the 32-bit shift patterns of HC11 by breaking
the match_dup that is required by these patterns (they have been defined to
reduce the number of operands for the reload; otherwise reload can fail).
Since the web optimisation does not check the validity of its changes, the resulting
insn are no longer recognized and I come up with:

gcc.c-torture/compile/20010102-1.c:101: error: unrecognizable insn: (insn:HI 109 108 110 16 (parallel [ (set (reg:SI 130 [ i ]) (ashift:SI (reg:SI 85 [ i ]) (const_int 2 [0x2]))) (clobber (scratch:HI)) ]) -1 (insn_list 108 (nil)) (expr_list:REG_DEAD (reg:SI 85 [ i ]) (expr_list:REG_UNUSED (scratch:HI) (expr_list:REG_EQUAL (ashift:SI (reg:SI 82 [ i ]) (const_int 2 [0x2])) (nil)))))

In this extract, the web changed operand 0 from (reg:SI 85) to (reg:SI 130).

I've committed this patch on 3_4 to disable -fweb on 68hc11 (was activated by -O3).


2004-03-03 Stephane Carrez <>

	* config/m68hc11/m68hc11.c (m68hc11_override_options): Disable -fweb
	because it breaks the 32-bit shift patterns that rely on a match_dup.
	(print_operand): Don't print a * before the base address.

Index: config/m68hc11/m68hc11.c
RCS file: /cvs/gcc/gcc/gcc/config/m68hc11/m68hc11.c,v
retrieving revision
diff -u -p -r1.91.6.2 m68hc11.c
--- config/m68hc11/m68hc11.c	2 Mar 2004 22:34:02 -0000
+++ config/m68hc11/m68hc11.c	3 Mar 2004 21:42:29 -0000
@@ -282,6 +282,11 @@ m68hc11_override_options (void)
       flag_pic = 0;
+  /* Do not enable -fweb because it breaks the 32-bit shift patterns
+     by breaking the match_dup of those patterns.  The shift patterns
+     will no longer be recognized after that.  */
+  flag_web = 0;
   /* Configure for a 68hc11 processor.  */
   if (TARGET_M6811)
@@ -2313,9 +2318,6 @@ print_operand (FILE *file, rtx op, int l
-          if (m68hc11_page0_symbol_p (base))
-            fprintf (file, "*");
 	  output_address (base);

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