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Re: [RFC] P6 microarch (Pentium 2/3) DFA scheduler description
Steven Bosscher <firstname.lastname@example.org> writes:
> On Thursday 26 February 2004 03:51, James Morrison wrote:
> > > to ! ;; two uops, and simple read-modify instructions also take two µops.
> > uops?
> Actually it is µops, but the mu symbol is usually typed as u for
> simplicity. This was probably copy-paste from some manual, but
> I should use uops everywhere.
> > > uop, ! ;; which is not exactly true because there are a few instructions
> > > that ! ;; decode to 2 uops or microcode. But this probably gives the
> > > best
> > What does microcode mean here?
> Microcode means that the sequence of uops generated for an
> instruction is hard-coded on the chip, i.e. firmware.
Would "a few instructions decode to 2 uops or more" work? Or are some
instructions not decoded using the microcode?
> > > ! ;; div and idiv are very similar, so we model them the same.
> > > ! ;; QI,HI,and SI have issue latency 12, 21, and 37, respectively.
> > The code has magic numbers 19, 23, 39. Is it obvious where the extra
> > 7, 2, and 2 are coming from?
> The difference of 7 is probably a typo, iirc the 12 should be 17.
> The 19, 23, and 39 are the latencies for the _result_ of the
> instruction, while the 17, 21, and 37 are the issue latencies,
> i.e. a new idiv can only be issued 17/21/37 cycles after the
> previous one.
> > Thanks, this was fun to read.
> Thanks for the corrections!