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Re: [RFC] P6 microarch (Pentium 2/3) DFA scheduler description
- From: Steven Bosscher <stevenb at suse dot de>
- To: James Morrison <ja2morri at csclub dot uwaterloo dot ca>
- Cc: gcc-patches at gcc dot gnu dot org, jh at suse dot cz, law at redhat dot com,vmakarov at redhat dot com
- Date: Thu, 26 Feb 2004 11:58:01 +0100
- Subject: Re: [RFC] P6 microarch (Pentium 2/3) DFA scheduler description
- Organization: SUSE Labs
- References: <email@example.com> <firstname.lastname@example.org>
On Thursday 26 February 2004 03:51, James Morrison wrote:
> > to ! ;; two uops, and simple read-modify instructions also take two µops.
Actually it is µops, but the mu symbol is usually typed as u for
simplicity. This was probably copy-paste from some manual, but
I should use uops everywhere.
> > uop, ! ;; which is not exactly true because there are a few instructions
> > that ! ;; decode to 2 uops or microcode. But this probably gives the
> > best
> What does microcode mean here?
Microcode means that the sequence of uops generated for an
instruction is hard-coded on the chip, i.e. firmware.
> > ! ;; div and idiv are very similar, so we model them the same.
> > ! ;; QI,HI,and SI have issue latency 12, 21, and 37, respectively.
> The code has magic numbers 19, 23, 39. Is it obvious where the extra
> 7, 2, and 2 are coming from?
The difference of 7 is probably a typo, iirc the 12 should be 17.
The 19, 23, and 39 are the latencies for the _result_ of the
instruction, while the 17, 21, and 37 are the issue latencies,
i.e. a new idiv can only be issued 17/21/37 cycles after the
> Thanks, this was fun to read.
Thanks for the corrections!