Patch [rs6000]: support FP modes in CTR/LR

[Dale Johannesen <dalej at apple dot com>]

Support was incomplete because, when you have a DF-pseudo-to-DF-pseudo 
copy, it
is possible for both sides to get assigned CTR or LR, and the hardfloat 
patterns
weren't accepting this.  (Oddly, the softfloat patterns were OK.)  This 
fixes it;
bootstrap in progress.  (Showed up building gap in SPEC2000, which I 
cannot
attach.)

Note that the CTR-to-LR case is not handled by any of the patterns, and
can't be without a temporary somewhere.    What I'd like to do is 
remove support
for keeping FP objects in CTR/LR (it looks like changing 
HARD_REGNO_MODE_OK
is sufficient); while it's possible to construct cases where this is 
useful, most of the
time the code is going to be really bad.  Does that seem like a 
reasonable idea?


Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.292
diff -u -d -b -w -c -3 -p -r1.292 rs6000.md
cvs server: conflicting specifications of output style
*** rs6000.md   19 Feb 2004 18:40:24 -0000      1.292
--- rs6000.md   20 Feb 2004 23:42:08 -0000
***************
*** 7888,7895 ****
  }")

  (define_insn "*movsf_hardfloat"
!   [(set (match_operand:SF 0 "nonimmediate_operand" 
"=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r")
!       (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))]
    "(gpc_reg_operand (operands[0], SFmode)
     || gpc_reg_operand (operands[1], SFmode))
     && (TARGET_HARD_FLOAT && TARGET_FPRS)"
--- 7888,7895 ----
  }")

  (define_insn "*movsf_hardfloat"
!   [(set (match_operand:SF 0 "nonimmediate_operand" 
"=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
!       (match_operand:SF 1 "input_operand" 
"r,m,r,f,m,f,r,r,h,0,G,Fn"))]
    "(gpc_reg_operand (operands[0], SFmode)
     || gpc_reg_operand (operands[1], SFmode))
     && (TARGET_HARD_FLOAT && TARGET_FPRS)"
***************
*** 7903,7912 ****
     mt%0 %1
     mt%0 %1
     mf%1 %0
     #
     #"
!   [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*")
!    (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])

  (define_insn "*movsf_softfloat"
    [(set (match_operand:SF 0 "nonimmediate_operand" 
"=r,cl,q,r,r,m,r,r,r,r,r,*h")
--- 7903,7913 ----
     mt%0 %1
     mt%0 %1
     mf%1 %0
+    nop
     #
     #"
!   [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
!    (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])

  (define_insn "*movsf_softfloat"
    [(set (match_operand:SF 0 "nonimmediate_operand" 
"=r,cl,q,r,r,m,r,r,r,r,r,*h")
***************
*** 8163,8170 ****
  ; ld/std require word-aligned displacements -> 'Y' constraint.
  ; List Y->r and r->Y before r->r for reload.
  (define_insn "*movdf_hardfloat64"
!   [(set (match_operand:DF 0 "nonimmediate_operand" 
"=Y,r,!r,f,f,m,!cl,!r,!r,!r,!r")
!       (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,G,H,F"))]
    "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
     && (gpc_reg_operand (operands[0], DFmode)
         || gpc_reg_operand (operands[1], DFmode))"
--- 8164,8171 ----
  ; ld/std require word-aligned displacements -> 'Y' constraint.
  ; List Y->r and r->Y before r->r for reload.
  (define_insn "*movdf_hardfloat64"
!   [(set (match_operand:DF 0 "nonimmediate_operand" 
"=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
!       (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
    "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
     && (gpc_reg_operand (operands[0], DFmode)
         || gpc_reg_operand (operands[1], DFmode))"
***************
*** 8177,8187 ****
     stfd%U0%X0 %1,%0
     mt%0 %1
     mf%1 %0
     #
     #
     #"
!   [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*")
!    (set_attr "length" "4,4,4,4,4,4,4,4,8,12,16")])

  (define_insn "*movdf_softfloat64"
    [(set (match_operand:DF 0 "nonimmediate_operand" 
"=r,Y,r,cl,r,r,r,r,*h")
--- 8178,8189 ----
     stfd%U0%X0 %1,%0
     mt%0 %1
     mf%1 %0
+    nop
     #
     #
     #"
!   [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
!    (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])

  (define_insn "*movdf_softfloat64"
    [(set (match_operand:DF 0 "nonimmediate_operand" 
"=r,Y,r,cl,r,r,r,r,*h")