This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
S/390: Fix (newly) non-canonical RTL
- From: Ulrich Weigand <weigand at i1 dot informatik dot uni-erlangen dot de>
- To: gcc-patches at gcc dot gnu dot org
- Date: Thu, 19 Feb 2004 00:02:09 +0100 (CET)
- Subject: S/390: Fix (newly) non-canonical RTL
Hello,
since this recent patch by Geoff Keating:
http://gcc.gnu.org/ml/gcc-patches/2004-02/msg01498.html
several insn patterns in the s390 backend expand to
non-canonical RTL, leading to dozens of test suite
failures.
This patch fixes the problem by rearranging the patterns
according to the new canonicalization rules.
Bootstrapped/regtested on s390-ibm-linux and s390x-ibm-linux.
Bye,
Ulrich
ChangeLog:
* config/s390/s390.md ("divmodtidi3"): Use canonical RTL.
("divmodtisi3"): Likewise.
("udivmoddi4", "udivmodtidi3"): Likewise.
("divmodsi4", "divmoddisi3"): Likewise.
("udivmodsi4", "udivmoddisi3"): Likewise.
("udivsi3", "umodsi3"): Likewise.
Index: gcc/config/s390/s390.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.md,v
retrieving revision 1.100
diff -c -p -r1.100 s390.md
*** gcc/config/s390/s390.md 13 Feb 2004 14:57:27 -0000 1.100
--- gcc/config/s390/s390.md 18 Feb 2004 17:54:12 -0000
***************
*** 4575,4588 ****
(define_insn "divmodtidi3"
[(set (match_operand:TI 0 "register_operand" "=d,d")
(ior:TI
- (zero_extend:TI
- (div:DI (match_operand:DI 1 "register_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,m")))
(ashift:TI
(zero_extend:TI
! (mod:DI (match_dup 1)
! (match_dup 2)))
! (const_int 64))))]
"TARGET_64BIT"
"@
dsgr\t%0,%2
--- 4575,4586 ----
(define_insn "divmodtidi3"
[(set (match_operand:TI 0 "register_operand" "=d,d")
(ior:TI
(ashift:TI
(zero_extend:TI
! (mod:DI (match_operand:DI 1 "register_operand" "0,0")
! (match_operand:DI 2 "general_operand" "d,m")))
! (const_int 64))
! (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
"TARGET_64BIT"
"@
dsgr\t%0,%2
***************
*** 4593,4606 ****
(define_insn "divmodtisi3"
[(set (match_operand:TI 0 "register_operand" "=d,d")
(ior:TI
- (zero_extend:TI
- (div:DI (match_operand:DI 1 "register_operand" "0,0")
- (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
(ashift:TI
(zero_extend:TI
! (mod:DI (match_dup 1)
! (sign_extend:DI (match_dup 2))))
! (const_int 64))))]
"TARGET_64BIT"
"@
dsgfr\t%0,%2
--- 4591,4604 ----
(define_insn "divmodtisi3"
[(set (match_operand:TI 0 "register_operand" "=d,d")
(ior:TI
(ashift:TI
(zero_extend:TI
! (mod:DI (match_operand:DI 1 "register_operand" "0,0")
! (sign_extend:DI
! (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
! (const_int 64))
! (zero_extend:TI
! (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
"TARGET_64BIT"
"@
dsgfr\t%0,%2
***************
*** 4626,4635 ****
div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
equal = gen_rtx_IOR (TImode,
- gen_rtx_ZERO_EXTEND (TImode, div_equal),
gen_rtx_ASHIFT (TImode,
gen_rtx_ZERO_EXTEND (TImode, mod_equal),
! GEN_INT (64)));
operands[4] = gen_reg_rtx(TImode);
emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
--- 4624,4633 ----
div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
equal = gen_rtx_IOR (TImode,
gen_rtx_ASHIFT (TImode,
gen_rtx_ZERO_EXTEND (TImode, mod_equal),
! GEN_INT (64)),
! gen_rtx_ZERO_EXTEND (TImode, div_equal));
operands[4] = gen_reg_rtx(TImode);
emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
***************
*** 4652,4667 ****
(define_insn "udivmodtidi3"
[(set (match_operand:TI 0 "register_operand" "=d,d")
! (ior:TI (zero_extend:TI
! (truncate:DI
! (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
! (zero_extend:TI
! (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
! (ashift:TI
! (zero_extend:TI
! (truncate:DI
! (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
! (const_int 64))))]
"TARGET_64BIT"
"@
dlgr\t%0,%2
--- 4650,4666 ----
(define_insn "udivmodtidi3"
[(set (match_operand:TI 0 "register_operand" "=d,d")
! (ior:TI
! (ashift:TI
! (zero_extend:TI
! (truncate:DI
! (umod:TI (match_operand:TI 1 "register_operand" "0,0")
! (zero_extend:TI
! (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
! (const_int 64))
! (zero_extend:TI
! (truncate:DI
! (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
"TARGET_64BIT"
"@
dlgr\t%0,%2
***************
*** 4687,4696 ****
div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
equal = gen_rtx_IOR (DImode,
- gen_rtx_ZERO_EXTEND (DImode, div_equal),
gen_rtx_ASHIFT (DImode,
gen_rtx_ZERO_EXTEND (DImode, mod_equal),
! GEN_INT (32)));
operands[4] = gen_reg_rtx(DImode);
emit_insn (gen_extendsidi2 (operands[4], operands[1]));
--- 4686,4695 ----
div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
equal = gen_rtx_IOR (DImode,
gen_rtx_ASHIFT (DImode,
gen_rtx_ZERO_EXTEND (DImode, mod_equal),
! GEN_INT (32)),
! gen_rtx_ZERO_EXTEND (DImode, div_equal));
operands[4] = gen_reg_rtx(DImode);
emit_insn (gen_extendsidi2 (operands[4], operands[1]));
***************
*** 4711,4726 ****
(define_insn "divmoddisi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
! (ior:DI (zero_extend:DI
! (truncate:SI
! (div:DI (match_operand:DI 1 "register_operand" "0,0")
! (sign_extend:DI
! (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
! (ashift:DI
! (zero_extend:DI
! (truncate:SI
! (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
! (const_int 32))))]
"!TARGET_64BIT"
"@
dr\t%0,%2
--- 4710,4726 ----
(define_insn "divmoddisi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
! (ior:DI
! (ashift:DI
! (zero_extend:DI
! (truncate:SI
! (mod:DI (match_operand:DI 1 "register_operand" "0,0")
! (sign_extend:DI
! (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
! (const_int 32))
! (zero_extend:DI
! (truncate:SI
! (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
"!TARGET_64BIT"
"@
dr\t%0,%2
***************
*** 4746,4755 ****
div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
equal = gen_rtx_IOR (DImode,
- gen_rtx_ZERO_EXTEND (DImode, div_equal),
gen_rtx_ASHIFT (DImode,
gen_rtx_ZERO_EXTEND (DImode, mod_equal),
! GEN_INT (32)));
operands[4] = gen_reg_rtx(DImode);
emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
--- 4746,4755 ----
div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
equal = gen_rtx_IOR (DImode,
gen_rtx_ASHIFT (DImode,
gen_rtx_ZERO_EXTEND (DImode, mod_equal),
! GEN_INT (32)),
! gen_rtx_ZERO_EXTEND (DImode, div_equal));
operands[4] = gen_reg_rtx(DImode);
emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
***************
*** 4772,4787 ****
(define_insn "udivmoddisi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
! (ior:DI (zero_extend:DI
! (truncate:SI
! (udiv:DI (match_operand:DI 1 "register_operand" "0,0")
! (zero_extend:DI
! (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
! (ashift:DI
! (zero_extend:DI
! (truncate:SI
! (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
! (const_int 32))))]
"!TARGET_64BIT && TARGET_CPU_ZARCH"
"@
dlr\t%0,%2
--- 4772,4788 ----
(define_insn "udivmoddisi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
! (ior:DI
! (ashift:DI
! (zero_extend:DI
! (truncate:SI
! (umod:DI (match_operand:DI 1 "register_operand" "0,0")
! (zero_extend:DI
! (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
! (const_int 32))
! (zero_extend:DI
! (truncate:SI
! (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
"!TARGET_64BIT && TARGET_CPU_ZARCH"
"@
dlr\t%0,%2
***************
*** 4801,4810 ****
udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
equal = gen_rtx_IOR (DImode,
- gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
gen_rtx_ASHIFT (DImode,
gen_rtx_ZERO_EXTEND (DImode, umod_equal),
! GEN_INT (32)));
operands[3] = gen_reg_rtx (DImode);
--- 4802,4811 ----
udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
equal = gen_rtx_IOR (DImode,
gen_rtx_ASHIFT (DImode,
gen_rtx_ZERO_EXTEND (DImode, umod_equal),
! GEN_INT (32)),
! gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
operands[3] = gen_reg_rtx (DImode);
***************
*** 4892,4901 ****
udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
equal = gen_rtx_IOR (DImode,
- gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
gen_rtx_ASHIFT (DImode,
gen_rtx_ZERO_EXTEND (DImode, umod_equal),
! GEN_INT (32)));
operands[3] = gen_reg_rtx (DImode);
--- 4893,4902 ----
udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
equal = gen_rtx_IOR (DImode,
gen_rtx_ASHIFT (DImode,
gen_rtx_ZERO_EXTEND (DImode, umod_equal),
! GEN_INT (32)),
! gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
operands[3] = gen_reg_rtx (DImode);
--
Dr. Ulrich Weigand
weigand@informatik.uni-erlangen.de