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[patch] h8300: Don't generate insns by hand. (part 3)
- From: Kazu Hirata <kazu at cs dot umass dot edu>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 17 Feb 2004 18:44:31 -0500 (EST)
- Subject: [patch] h8300: Don't generate insns by hand. (part 3)
Hi,
Attached is a patch to have fix_bit_operand() call the expanders
generated from h8300.md instead of generating insns by hand.
The purpose of this patch is to make the MODE_CC conversion easier.
Tested on h8300-elf. Committed.
Kazu Hirata
2004-02-17 Kazu Hirata <kazu@cs.umass.edu>
* config/h8300/h8300.c (fix_bit_operand): Don't generate insns
by hand.
* config/h8300/h8300.md (*andqi3_1): Change to andqi3_1.
(*iorqi3_1): Change to iorqi3_1.
(*xorqi3_1): Change to xorqi3_1.
Index: h8300.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.c,v
retrieving revision 1.274
diff -u -r1.274 h8300.c
--- h8300.c 10 Feb 2004 23:58:57 -0000 1.274
+++ h8300.c 16 Feb 2004 04:10:47 -0000
@@ -4103,10 +4103,21 @@
operands[1] = force_reg (QImode, operands[1]);
{
rtx res = gen_reg_rtx (QImode);
- emit_insn (gen_rtx_SET (VOIDmode, res,
- gen_rtx_fmt_ee (type, QImode,
- operands[1], operands[2])));
- emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
+ switch (type)
+ {
+ case AND:
+ emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
+ break;
+ case IOR:
+ emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
+ break;
+ case XOR:
+ emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
+ break;
+ default:
+ abort ();
+ }
+ emit_insn (gen_movqi (operands[0], res));
}
return 1;
}
Index: h8300.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.md,v
retrieving revision 1.265
diff -u -r1.265 h8300.md
--- h8300.md 16 Feb 2004 03:53:38 -0000 1.265
+++ h8300.md 16 Feb 2004 04:10:56 -0000
@@ -1183,7 +1183,7 @@
;; AND INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "*andqi3_1"
+(define_insn "andqi3_1"
[(set (match_operand:QI 0 "bit_operand" "=r,U")
(and:QI (match_operand:QI 1 "bit_operand" "%0,0")
(match_operand:QI 2 "nonmemory_operand" "rn,n")))]
@@ -1279,7 +1279,7 @@
;; OR INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "*iorqi3_1"
+(define_insn "iorqi3_1"
[(set (match_operand:QI 0 "bit_operand" "=r,U")
(ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
(match_operand:QI 2 "nonmemory_operand" "rn,n")))]
@@ -1320,7 +1320,7 @@
;; XOR INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "*xorqi3_1"
+(define_insn "xorqi3_1"
[(set (match_operand:QI 0 "bit_operand" "=r,U")
(xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
(match_operand:QI 2 "nonmemory_operand" "rn,n")))]