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Re: Fix PR target/14113


Quoting Eric Botcazou <ebotcazou@libertysurf.fr>:

> This is a case in which a C++ exception is not caught on SPARC at -O2, a 
> regression from GCC 2.95.3 present on the 3.3 branch.
> 
> The culprits are the last 2 remaining peepholes of the SPARC port, that I 
> have already scrapped for GCC 3.4:
> 
> ;; Now peepholes to do a call followed by a jump.
> 
> (define_peephole
>   [(parallel [(set (match_operand 0 "" "")
> 		   (call (mem:SI (match_operand:SI 1 "call_operand_address" "ps"))
> 			 (match_operand 2 "" "")))
> 	      (clobber (reg:SI 15))])
>    (set (pc) (label_ref (match_operand 3 "" "")))]
>   "short_branch (INSN_UID (insn), INSN_UID (operands[3]))
>    && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1))
>    && sparc_cpu != PROCESSOR_ULTRASPARC
>    && sparc_cpu != PROCESSOR_ULTRASPARC3"
>   "call\t%a1, %2\n\tadd\t%%o7, (%l3-.-4), %%o7")
> 
> (define_peephole
>   [(parallel [(call (mem:SI (match_operand:SI 0 "call_operand_address"
> "ps"))
> 		    (match_operand 1 "" ""))
> 	      (clobber (reg:SI 15))])
>    (set (pc) (label_ref (match_operand 2 "" "")))]
>   "short_branch (INSN_UID (insn), INSN_UID (operands[2]))
>    && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1))
>    && sparc_cpu != PROCESSOR_ULTRASPARC
>    && sparc_cpu != PROCESSOR_ULTRASPARC3"
>   "call\t%a0, %1\n\tadd\t%%o7, (%l2-.-4), %%o7")
> 
> 
> They change the value of the PC return register without updating the CFIs, so
> 
> the unwind mechanism is fooled.
> 
> 
> Gaby, may I put the patch on the 3.3 branch, after the usual testing?  The PR

Given that it is localized and you test on the supported plateforms, yes
it is OK.  Please send a note to Joe for inclusion in the release note.

Thanks!

> 
> was opened a few hours ago, this is an important issue and the patch is the 
> safest last minute patch you can dream of :-)
> 
> 
> 2004-02-11  Eric Botcazou  <ebotcazou@libertysurf.fr>
> 
> 	PR target/14113
> 	* config/sparc/sparc.md (2 define_peepholes): Remove.
> 
> 
> -- 
> Eric Botcazou




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