This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [PATCH] Support signbit, signbitf and signbitl as GCC builtins
- From: Roger Sayle <roger at eyesopen dot com>
- To: Ulrich Weigand <weigand at i1 dot informatik dot uni-erlangen dot de>
- Cc: rth at redhat dot com, <gcc-patches at gcc dot gnu dot org>
- Date: Wed, 4 Feb 2004 18:47:52 -0700 (MST)
- Subject: Re: [PATCH] Support signbit, signbitf and signbitl as GCC builtins
On Thu, 5 Feb 2004, Ulrich Weigand wrote:
> Well, the 'test' routine of builtins-32.c generates the following code
> before reload (24.lreg):
>
> ...
>
> (insn 11 3 13 0 (set (reg:SI 43)
> (subreg:SI (reg/v:DF 41 [ x ]) 0)) 54 {*movsi_zarch} (insn_list 3 (nil))
> (expr_list:REG_DEAD (reg/v:DF 41 [ x ])
> (nil)))
How does this RTL match the constraints for movsi_zarch pattern?
> Note how insn 32 is broken? It simply reinterprets reg %r1 in SImode,
> and hence loads the *low* half of the register into %r3. In fact to
> do it right would require either a shift (which reload never does) or
> else *another* secondary memory slot.
As you explain above, performing this operation in RTL requires either
a shift or an additional memory slot, so I'm surprised that the s390
backend claims it can be done using a plain movsi_zarch. Perhaps if
the SUBREG_BYTE was 4...
Forgive me, I'm out of my depth with backend machine descriptions.
But it looks as though the constraints for movsi_zarch claim that
it can perform the necessary subreg without the help of reload.
Roger
--