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Fix code assembling for UltraSPARC III on Solaris
- From: Eric Botcazou <ebotcazou at libertysurf dot fr>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sun, 1 Feb 2004 16:26:00 +0100
- Subject: Fix code assembling for UltraSPARC III on Solaris
My recent overhaul of the SPARC options made me realize that there is a big
problem with 32-bit code generation for UltraSPARC III on Solaris: the code
can't be assembled. *sigh*
poog% gcc/xgcc -Bgcc -c t.c -m32 -mcpu=ultrasparc3
/usr/ccs/bin/as: "/var/tmp//cceNxUlq.s", line 17: error: cannot use v8plus
instructions in a non-v8plus target binary
The problem is that GCC generates SPARC-V8+ code by default on Solaris in
32-bit mode for all SPARC-V9 processors, but doesn't say it to the assembler
for UltraSPARC III. Hence it complains.
Fixed by the attached patch, tested on sparc64-sun-solaris2.9, applied to
mainline and 3.4 branch.
2004-02-01 Eric Botcazou <ebotcazou@libertysurf.fr>
* config/sparc/sol2-bi.h: Handle TARGET_CPU_ultrasparc3.
(CPP_CPU_SPEC): Handle -mcpu=ultrasparc3.
(ASM_CPU_SPEC): Likewise
* config/sparc/sol2.h: Handle TARGET_CPU_ultrasparc3.
(ASM_CPU_SPEC): Remove -mcpu=v8plus. Handle -mcpu=ultrasparc3.
--
Eric Botcazou
Index: config/sparc/sol2-bi.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sol2-bi.h,v
retrieving revision 1.14
diff -u -r1.14 sol2-bi.h
--- config/sparc/sol2-bi.h 20 Dec 2003 07:40:22 -0000 1.14
+++ config/sparc/sol2-bi.h 31 Jan 2004 21:23:59 -0000
@@ -18,6 +18,7 @@
#undef ASM_CPU32_DEFAULT_SPEC
#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plus"
#endif
+
#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
#undef CPP_CPU64_DEFAULT_SPEC
#define CPP_CPU64_DEFAULT_SPEC ""
@@ -27,6 +28,15 @@
#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "a"
#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
+#undef CPP_CPU64_DEFAULT_SPEC
+#define CPP_CPU64_DEFAULT_SPEC ""
+#undef ASM_CPU32_DEFAULT_SPEC
+#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb"
+#undef ASM_CPU64_DEFAULT_SPEC
+#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
+#endif
+
#if DEFAULT_ARCH32_P
#define DEF_ARCH32_SPEC(__str) "%{!m64:" __str "}"
#define DEF_ARCH64_SPEC(__str) "%{m64:" __str "}"
@@ -45,15 +55,16 @@
%{mcpu=sparclite|mcpu-f930|mcpu=f934:-D__sparclite__} \
%{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
%{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \
-%{mcpu=v9|mcpu=ultrasparc:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
+%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
"
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC "\
-%{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-xarch=v8plusa") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "a") "} \
%{mcpu=v9:" DEF_ARCH32_SPEC("-xarch=v8plus") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "} \
-%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}} \
+%{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-xarch=v8plusa") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "a") "} \
+%{mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \
+%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}} \
%{!mcpu*:%(asm_cpu_default)} \
"
Index: config/sparc/sol2.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sol2.h,v
retrieving revision 1.58
diff -u -r1.58 sol2.h
--- config/sparc/sol2.h 19 Jan 2004 16:57:05 -0000 1.58
+++ config/sparc/sol2.h 31 Jan 2004 21:24:00 -0000
@@ -36,11 +36,16 @@
#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusa"
#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
+#undef ASM_CPU_DEFAULT_SPEC
+#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb"
+#endif
+
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC "\
-%{mcpu=v8plus:-xarch=v8plus} \
%{mcpu=v9:-xarch=v8plus} \
%{mcpu=ultrasparc:-xarch=v8plusa} \
+%{mcpu=ultrasparc3:-xarch=v8plusb} \
%{!mcpu*:%(asm_cpu_default)} \
"