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[3.4/head] fix alphaev5 compat/scalar-return-4
- From: Richard Henderson <rth at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Mon, 19 Jan 2004 12:36:15 -0800
- Subject: [3.4/head] fix alphaev5 compat/scalar-return-4
Problem here is that generating subregs in .md file patterns
is almost always a bug. Indeed, here we created
(subreg:DI (subreg:HI (reg:CHI xx) 0) 0)
This will never get recognized.
r~
* config/alpha/alpha.c (alpha_expand_mov_nobwx): If the destination
is not a reg, copy to a scratch first.
(aligned_loadqi, aligned_loadhi, unaligned_loadqi, unaligned_loadhi,
unaligned_loadqi_le, unaligned_loadqi_be, unaligned_loadhi_le,
unaligned_loadhi_be): Expect op0 in DImode; don't SUBREG.
(reload_inqi, reload_inhi): Fix mode of op0.
(reload_inqi_help, reload_inhi_help, reload_outqi_help,
reload_outhi_help): Likewise. Use define_insn_and_split.
Index: alpha.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.c,v
retrieving revision 1.342.4.1
diff -c -p -d -r1.342.4.1 alpha.c
*** alpha.c 19 Jan 2004 09:53:45 -0000 1.342.4.1
--- alpha.c 19 Jan 2004 19:36:28 -0000
*************** alpha_expand_mov_nobwx (enum machine_mod
*** 2876,2888 ****
{
rtx aligned_mem, bitnum;
rtx scratch = gen_reg_rtx (SImode);
get_aligned_mem (operands[1], &aligned_mem, &bitnum);
emit_insn ((mode == QImode
? gen_aligned_loadqi
: gen_aligned_loadhi)
! (operands[0], aligned_mem, bitnum, scratch));
}
}
else
--- 2878,2901 ----
{
rtx aligned_mem, bitnum;
rtx scratch = gen_reg_rtx (SImode);
+ rtx subtarget;
+ bool copyout;
get_aligned_mem (operands[1], &aligned_mem, &bitnum);
+ subtarget = operands[0];
+ if (GET_CODE (subtarget) == REG)
+ subtarget = gen_lowpart (DImode, subtarget), copyout = false;
+ else
+ subtarget = gen_reg_rtx (DImode), copyout = true;
+
emit_insn ((mode == QImode
? gen_aligned_loadqi
: gen_aligned_loadhi)
! (subtarget, aligned_mem, bitnum, scratch));
!
! if (copyout)
! emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
}
}
else
*************** alpha_expand_mov_nobwx (enum machine_mod
*** 2891,2906 ****
code depend on parameter evaluation order which will cause
bootstrap failures. */
! rtx temp1 = gen_reg_rtx (DImode);
! rtx temp2 = gen_reg_rtx (DImode);
! rtx seq = ((mode == QImode
! ? gen_unaligned_loadqi
! : gen_unaligned_loadhi)
! (operands[0], get_unaligned_address (operands[1], 0),
! temp1, temp2));
alpha_set_memflags (seq, operands[1]);
emit_insn (seq);
}
return true;
}
--- 2904,2931 ----
code depend on parameter evaluation order which will cause
bootstrap failures. */
! rtx temp1, temp2, seq, subtarget;
! bool copyout;
!
! temp1 = gen_reg_rtx (DImode);
! temp2 = gen_reg_rtx (DImode);
!
! subtarget = operands[0];
! if (GET_CODE (subtarget) == REG)
! subtarget = gen_lowpart (DImode, subtarget), copyout = false;
! else
! subtarget = gen_reg_rtx (DImode), copyout = true;
+ seq = ((mode == QImode
+ ? gen_unaligned_loadqi
+ : gen_unaligned_loadhi)
+ (subtarget, get_unaligned_address (operands[1], 0),
+ temp1, temp2));
alpha_set_memflags (seq, operands[1]);
emit_insn (seq);
+
+ if (copyout)
+ emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
}
return true;
}
Index: alpha.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.md,v
retrieving revision 1.215.6.1
diff -c -p -d -r1.215.6.1 alpha.md
*** alpha.md 19 Jan 2004 09:53:46 -0000 1.215.6.1
--- alpha.md 19 Jan 2004 19:36:28 -0000
***************
*** 5708,5714 ****
(define_expand "aligned_loadqi"
[(set (match_operand:SI 3 "register_operand" "")
(match_operand:SI 1 "memory_operand" ""))
! (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
(zero_extract:DI (subreg:DI (match_dup 3) 0)
(const_int 8)
(match_operand:DI 2 "const_int_operand" "")))]
--- 5710,5716 ----
(define_expand "aligned_loadqi"
[(set (match_operand:SI 3 "register_operand" "")
(match_operand:SI 1 "memory_operand" ""))
! (set (match_operand:DI 0 "register_operand" "")
(zero_extract:DI (subreg:DI (match_dup 3) 0)
(const_int 8)
(match_operand:DI 2 "const_int_operand" "")))]
***************
*** 5719,5725 ****
(define_expand "aligned_loadhi"
[(set (match_operand:SI 3 "register_operand" "")
(match_operand:SI 1 "memory_operand" ""))
! (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
(zero_extract:DI (subreg:DI (match_dup 3) 0)
(const_int 16)
(match_operand:DI 2 "const_int_operand" "")))]
--- 5721,5727 ----
(define_expand "aligned_loadhi"
[(set (match_operand:SI 3 "register_operand" "")
(match_operand:SI 1 "memory_operand" ""))
! (set (match_operand:DI 0 "register_operand" "")
(zero_extract:DI (subreg:DI (match_dup 3) 0)
(const_int 16)
(match_operand:DI 2 "const_int_operand" "")))]
***************
*** 5735,5741 ****
;; operand 3 can overlap the input and output registers.
(define_expand "unaligned_loadqi"
! [(use (match_operand:QI 0 "register_operand" ""))
(use (match_operand:DI 1 "address_operand" ""))
(use (match_operand:DI 2 "register_operand" ""))
(use (match_operand:DI 3 "register_operand" ""))]
--- 5737,5743 ----
;; operand 3 can overlap the input and output registers.
(define_expand "unaligned_loadqi"
! [(use (match_operand:DI 0 "register_operand" ""))
(use (match_operand:DI 1 "address_operand" ""))
(use (match_operand:DI 2 "register_operand" ""))
(use (match_operand:DI 3 "register_operand" ""))]
***************
*** 5756,5762 ****
(const_int -8))))
(set (match_operand:DI 3 "register_operand" "")
(match_dup 1))
! (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
(zero_extract:DI (match_dup 2)
(const_int 8)
(ashift:DI (match_dup 3) (const_int 3))))]
--- 5758,5764 ----
(const_int -8))))
(set (match_operand:DI 3 "register_operand" "")
(match_dup 1))
! (set (match_operand:DI 0 "register_operand" "")
(zero_extract:DI (match_dup 2)
(const_int 8)
(ashift:DI (match_dup 3) (const_int 3))))]
***************
*** 5769,5775 ****
(const_int -8))))
(set (match_operand:DI 3 "register_operand" "")
(match_dup 1))
! (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
(zero_extract:DI (match_dup 2)
(const_int 8)
(minus:DI
--- 5771,5777 ----
(const_int -8))))
(set (match_operand:DI 3 "register_operand" "")
(match_dup 1))
! (set (match_operand:DI 0 "register_operand" "")
(zero_extract:DI (match_dup 2)
(const_int 8)
(minus:DI
***************
*** 5779,5785 ****
"")
(define_expand "unaligned_loadhi"
! [(use (match_operand:QI 0 "register_operand" ""))
(use (match_operand:DI 1 "address_operand" ""))
(use (match_operand:DI 2 "register_operand" ""))
(use (match_operand:DI 3 "register_operand" ""))]
--- 5781,5787 ----
"")
(define_expand "unaligned_loadhi"
! [(use (match_operand:DI 0 "register_operand" ""))
(use (match_operand:DI 1 "address_operand" ""))
(use (match_operand:DI 2 "register_operand" ""))
(use (match_operand:DI 3 "register_operand" ""))]
***************
*** 5800,5806 ****
(const_int -8))))
(set (match_operand:DI 3 "register_operand" "")
(match_dup 1))
! (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
(zero_extract:DI (match_dup 2)
(const_int 16)
(ashift:DI (match_dup 3) (const_int 3))))]
--- 5802,5808 ----
(const_int -8))))
(set (match_operand:DI 3 "register_operand" "")
(match_dup 1))
! (set (match_operand:DI 0 "register_operand" "")
(zero_extract:DI (match_dup 2)
(const_int 16)
(ashift:DI (match_dup 3) (const_int 3))))]
***************
*** 5813,5819 ****
(const_int -8))))
(set (match_operand:DI 3 "register_operand" "")
(plus:DI (match_dup 1) (const_int 1)))
! (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
(zero_extract:DI (match_dup 2)
(const_int 16)
(minus:DI
--- 5815,5821 ----
(const_int -8))))
(set (match_operand:DI 3 "register_operand" "")
(plus:DI (match_dup 1) (const_int 1)))
! (set (match_operand:DI 0 "register_operand" "")
(zero_extract:DI (match_dup 2)
(const_int 16)
(minus:DI
--- 6010,6015 ----
***************
*** 6029,6036 ****
scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
addr = get_unaligned_address (operands[1], 0);
! seq = gen_unaligned_loadqi (operands[0], addr, scratch,
! gen_rtx_REG (DImode, REGNO (operands[0])));
alpha_set_memflags (seq, operands[1]);
}
emit_insn (seq);
--- 6028,6035 ----
scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
addr = get_unaligned_address (operands[1], 0);
! operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
! seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]);
alpha_set_memflags (seq, operands[1]);
}
emit_insn (seq);
***************
*** 6066,6073 ****
scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
addr = get_unaligned_address (operands[1], 0);
! seq = gen_unaligned_loadhi (operands[0], addr, scratch,
! gen_rtx_REG (DImode, REGNO (operands[0])));
alpha_set_memflags (seq, operands[1]);
}
emit_insn (seq);
--- 6062,6069 ----
scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
addr = get_unaligned_address (operands[1], 0);
! operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
! seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]);
alpha_set_memflags (seq, operands[1]);
}
emit_insn (seq);
***************
*** 6148,6218 ****
;; always get a proper address for a stack slot during reload_foo
;; expansion, so we must delay our address manipulations until after.
! (define_insn "reload_inqi_help"
[(set (match_operand:QI 0 "register_operand" "=r")
(match_operand:QI 1 "memory_operand" "m"))
(clobber (match_operand:SI 2 "register_operand" "=r"))]
"! TARGET_BWX && (reload_in_progress || reload_completed)"
! "#")
!
! (define_insn "reload_inhi_help"
! [(set (match_operand:HI 0 "register_operand" "=r")
! (match_operand:HI 1 "memory_operand" "m"))
! (clobber (match_operand:SI 2 "register_operand" "=r"))]
! "! TARGET_BWX && (reload_in_progress || reload_completed)"
! "#")
!
! (define_insn "reload_outqi_help"
! [(set (match_operand:QI 0 "memory_operand" "=m")
! (match_operand:QI 1 "register_operand" "r"))
! (clobber (match_operand:SI 2 "register_operand" "=r"))
! (clobber (match_operand:SI 3 "register_operand" "=r"))]
! "! TARGET_BWX && (reload_in_progress || reload_completed)"
! "#")
!
! (define_insn "reload_outhi_help"
! [(set (match_operand:HI 0 "memory_operand" "=m")
! (match_operand:HI 1 "register_operand" "r"))
! (clobber (match_operand:SI 2 "register_operand" "=r"))
! (clobber (match_operand:SI 3 "register_operand" "=r"))]
! "! TARGET_BWX && (reload_in_progress || reload_completed)"
! "#")
!
! (define_split
! [(set (match_operand:QI 0 "register_operand" "")
! (match_operand:QI 1 "memory_operand" ""))
! (clobber (match_operand:SI 2 "register_operand" ""))]
"! TARGET_BWX && reload_completed"
[(const_int 0)]
{
rtx aligned_mem, bitnum;
get_aligned_mem (operands[1], &aligned_mem, &bitnum);
!
emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
operands[2]));
DONE;
})
! (define_split
! [(set (match_operand:HI 0 "register_operand" "")
! (match_operand:HI 1 "memory_operand" ""))
! (clobber (match_operand:SI 2 "register_operand" ""))]
"! TARGET_BWX && reload_completed"
[(const_int 0)]
{
rtx aligned_mem, bitnum;
get_aligned_mem (operands[1], &aligned_mem, &bitnum);
!
emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
operands[2]));
DONE;
})
! (define_split
! [(set (match_operand:QI 0 "memory_operand" "")
! (match_operand:QI 1 "register_operand" ""))
! (clobber (match_operand:SI 2 "register_operand" ""))
! (clobber (match_operand:SI 3 "register_operand" ""))]
"! TARGET_BWX && reload_completed"
[(const_int 0)]
{
--- 6138,6184 ----
;; always get a proper address for a stack slot during reload_foo
;; expansion, so we must delay our address manipulations until after.
! (define_insn_and_split "reload_inqi_help"
[(set (match_operand:QI 0 "register_operand" "=r")
(match_operand:QI 1 "memory_operand" "m"))
(clobber (match_operand:SI 2 "register_operand" "=r"))]
"! TARGET_BWX && (reload_in_progress || reload_completed)"
! "#"
"! TARGET_BWX && reload_completed"
[(const_int 0)]
{
rtx aligned_mem, bitnum;
get_aligned_mem (operands[1], &aligned_mem, &bitnum);
! operands[0] = gen_lowpart (DImode, operands[0]);
emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
operands[2]));
DONE;
})
! (define_insn_and_split "reload_inhi_help"
! [(set (match_operand:HI 0 "register_operand" "=r")
! (match_operand:HI 1 "memory_operand" "m"))
! (clobber (match_operand:SI 2 "register_operand" "=r"))]
! "! TARGET_BWX && (reload_in_progress || reload_completed)"
! "#"
"! TARGET_BWX && reload_completed"
[(const_int 0)]
{
rtx aligned_mem, bitnum;
get_aligned_mem (operands[1], &aligned_mem, &bitnum);
! operands[0] = gen_lowpart (DImode, operands[0]);
emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
operands[2]));
DONE;
})
! (define_insn_and_split "reload_outqi_help"
! [(set (match_operand:QI 0 "memory_operand" "=m")
! (match_operand:QI 1 "register_operand" "r"))
! (clobber (match_operand:SI 2 "register_operand" "=r"))
! (clobber (match_operand:SI 3 "register_operand" "=r"))]
! "! TARGET_BWX && (reload_in_progress || reload_completed)"
! "#"
"! TARGET_BWX && reload_completed"
[(const_int 0)]
{
***************
*** 6223,6233 ****
DONE;
})
! (define_split
! [(set (match_operand:HI 0 "memory_operand" "")
! (match_operand:HI 1 "register_operand" ""))
! (clobber (match_operand:SI 2 "register_operand" ""))
! (clobber (match_operand:SI 3 "register_operand" ""))]
"! TARGET_BWX && reload_completed"
[(const_int 0)]
{
--- 6189,6201 ----
DONE;
})
! (define_insn_and_split "reload_outhi_help"
! [(set (match_operand:HI 0 "memory_operand" "=m")
! (match_operand:HI 1 "register_operand" "r"))
! (clobber (match_operand:SI 2 "register_operand" "=r"))
! (clobber (match_operand:SI 3 "register_operand" "=r"))]
! "! TARGET_BWX && (reload_in_progress || reload_completed)"
! "#"
"! TARGET_BWX && reload_completed"
[(const_int 0)]
{