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Re: [PATCH] Fix another problem with RTX_UNCHANGING_P


> (insn 18 17 29 0 (set (mem/s/u:SI (plus:SI (reg/f:SI %eframe)
>                 (const_int -24 [0xffffffe8])) [6 y+8 S4 A64])
>         (reg/v/f:SI 59 [ x ])) 36 {*movsi_1} (nil)
>     (nil))
>
> (note /u in the last insn).  This violates RTX_UNCHANGING_P, since
> the memory at eframe-24 is written more than once and sched2 happily
> moves insn 18 before insn 17.

The patch is not sufficient because it clears the /u flag on only one of the 
MEMs.  Your testcase fails on SPARC with your patch applied, but didn't fail 
without your patch so we have a regression.

Before your patch:

(insn 12 10 13 (set (reg:DI 109)
        (const_int 0 [0x0])) -1 (nil)
    (nil))

(insn 13 12 14 (set (mem/s/u:DI (plus:SI (reg/f:SI 103 virtual-stack-vars)
                (const_int -24 [0xffffffffffffffe8])) [3 y+0 S8 A64])
        (reg:DI 109)) -1 (nil)
    (nil))

(insn 14 13 15 (set (reg:DI 110)
        (const_int 0 [0x0])) -1 (nil)
    (nil))

(insn 15 14 16 (set (mem/s/u:DI (plus:SI (reg/f:SI 103 virtual-stack-vars)
                (const_int -16 [0xfffffffffffffff0])) [3 y+8 S8 A64])
        (reg:DI 110)) -1 (nil)
    (nil))

(insn 16 15 17 (set (mem/s/u:SI (plus:SI (reg/f:SI 103 virtual-stack-vars)
                (const_int -8 [0xfffffffffffffff8])) [3 y+16 S4 A64])
        (const_int 0 [0x0])) -1 (nil)
    (nil))

(insn 17 16 19 (set (mem/s/u:SI (plus:SI (reg/f:SI 103 virtual-stack-vars)
                (const_int -16 [0xfffffffffffffff0])) [2 y+8 S4 A64])
        (reg/v/f:SI 108 [ x ])) -1 (nil)
    (nil))

After:

(insn 12 10 13 (set (reg:DI 109)
        (const_int 0 [0x0])) -1 (nil)
    (nil))

(insn 13 12 14 (set (mem/s/u:DI (plus:SI (reg/f:SI 103 virtual-stack-vars)
                (const_int -24 [0xffffffffffffffe8])) [3 y+0 S8 A64])
        (reg:DI 109)) -1 (nil)
    (nil))

(insn 14 13 15 (set (reg:DI 110)
        (const_int 0 [0x0])) -1 (nil)
    (nil))

(insn 15 14 16 (set (mem/s/u:DI (plus:SI (reg/f:SI 103 virtual-stack-vars)
                (const_int -16 [0xfffffffffffffff0])) [3 y+8 S8 A64])
        (reg:DI 110)) -1 (nil)
    (nil))

(insn 16 15 17 (set (mem/s/u:SI (plus:SI (reg/f:SI 103 virtual-stack-vars)
                (const_int -8 [0xfffffffffffffff8])) [3 y+16 S4 A64])
        (const_int 0 [0x0])) -1 (nil)
    (nil))

(insn 17 16 19 (set (mem/s:SI (plus:SI (reg/f:SI 103 virtual-stack-vars)
                (const_int -16 [0xfffffffffffffff0])) [2 y+8 S4 A64])
        (reg/v/f:SI 108 [ x ])) -1 (nil)
    (nil))

and sched2 swaps insn 15 and 17.

-- 
Eric Botcazou


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