This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[csl-asm?] PR middle-end/11821: Tweak arm_rtx_costs_1

The following patch is my proposed solution to PR middle-end/11821.
The problem is that GCC currently attempts to inline "x % 5" on the
ARM even when optimizing for size.  This is a problem because the
inlined instruction sequence is larger than the call to gcclib's
__modsi3 that would have been used otherwise.

It transpires that GCC's middle-end already contains the necessary
logic to determine whether inlining these operations should be a
win or not, but unfortunately the ARM backend is currently returning
"inaccurate" information which leads GCC to believe inlining to be
a win.  The real problem is that surprisingly the ARM backend's
RTX_COSTS completely ignores optimize_size (unlike many other targets)
and instead always returns cycle counts rather than the instruction
counts that are more appropriate for -Os.  The upshot is that inlining
always appears to be a win over a function call.

The near "obvious" fix below, is to return a more accurate estimate
of the size of a function call when optimizing for size.  This fixes
the testcase described in PR 11821, for example, we now inline "x % 4"
but emit a function call for "x % 5".  Using a cross-compiler to arm-elf,
this patch also shows a consistent improvement on CSiBE, which drops by
376 bytes from 1155445 to 1155069.  I'll leave the task of fine tuning
these parameters to the appropriate experts, as I don't have access to
an ARM machine myself.

Clearly, arm_rtx_costs_1 needs many further tweaks to accurately model
-Os compilation.  I suspect this may be one of the motivations for
CodeSourcery's ARM branch.  If not, this patch should atleast raise
the awareness of this issue amongst the ARM backend's maintainers.

The following patch has only been tested by building a cross compiler
from i686-pc-linux-gnu to arm-elf, for c, c++ and f77, and a full
testsuite run using arm-sim with no new failures (though the original
baseline run didn't look spectacularly healthy).

Even though this resolves a PR, the patch may be more appropriate for
the csl-arm branch than mainline?  I'll let the reviewer decide, but
if the verdict is csl-arm could someone apply this patch for me?

Very many thanks in advance,

2003-11-15  Roger Sayle  <>

	PR middle-end/11821
	* config/arm/arm.c (arm_rtx_costs_1): Improve estimate of the code
	size for calls to libgcc's div & mod subroutines when using -Os.

Index: arm.c
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.c,v
retrieving revision 1.306
diff -c -3 -p -r1.306 arm.c
*** arm.c	14 Nov 2003 10:41:47 -0000	1.306
--- arm.c	15 Nov 2003 21:18:56 -0000
*************** arm_rtx_costs_1 (rtx x, enum rtx_code co
*** 3210,3216 ****

      case DIV:
      case MOD:
!       return 100;

      case ROTATE:
        if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
--- 3210,3218 ----

      case DIV:
      case MOD:
!     case UDIV:
!     case UMOD:
!       return optimize_size ? COSTS_N_INSNS (2) : 100;

      case ROTATE:
        if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)

Roger Sayle,                         E-mail:
OpenEye Scientific Software,         WWW:
Suite 1107, 3600 Cerrillos Road,     Tel: (+1) 505-473-7385
Santa Fe, New Mexico, 87507.         Fax: (+1) 505-473-0833

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]