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Re: x86-64 XFmode long doubles


> > Jan Hubicka <hubicka@ucw.cz> writes:
> > 
> > >> Jan Hubicka <hubicka@ucw.cz> writes:
> > >> 
> > >> > Hi,
> > >> > the attached patch regoranize long doubles to use XFmodes and adds
> > >> > TFmode support as disucssed earlier.
> > >> 
> > >> Looks good...
> > >
> > > Good :)
> > > I guess I can approve it myself, so in case no one will complain and we
> > > get to agreemend wrt the symbol naming, I will commit it.
> > > It would be great if you could take closer look on the interface bits.
> > 
> > You're asking the wrong person, I'm not up on the issues.  I'd like
> > some opinions on the interface from the ia64 side of the fence,
> > myself.
> 
> OK.  At least if we switch two ports to the new interface, we will
> likely notice problems earlier :)  Thanks!

Hi,
since there does not appear to be any complains, I am commiting the
patch.  I am attaching revied version with some code duplication removed
and trivial fix to real.c to avoid uninitialized memory being output at
fourth word of 128-bit XFmode constants.  (I noticed this while
comparing assembly output from old and new compiler)

I guess we will soon work out whether we want to redirect the TFmode
calls or not, I will also dicuss the naming convention for 128-bit quad
emulation routines next week.

Honza

	* real.c (encode_ieee_extended): Initialize whole array.
	* reg-stack.c (move_for_stack_reg0: Use always XFmode.
	* i386-modes.def: Change definitions of TFmode and XFmode.
	* i386.c (classify_argument): Rename TFmodes to XFmodes; add new TFmode code.
	(construct_container): Allow constructing of TFmode integer containers.
	(ix86_return_in_memory):  XFmode is not returned in memory.
	(init_ext_80387_constants): Always use XFmode.
	(print_operand): Likewise.
	(ix86_prepare_fp_compare_regs): Likewise.
	(split_to_parts): Deal with TFmode.
	(split_long_move): Simplify.
	(ix86_init_mmx_sse_builtins): Add __float80, __float128.
	(ix86_memory_move_cost): Do not confuse TFmode.
	* i386.h (LONG_DOUBLE_TYPE_SIZE): Set to 96.
	(IS_STACK_MODE): TFmode is not stack mode.
	(HARD_REGNO_NREGS, CLASS_MAX_NREGS): Deal nicely with XFmode.
	(VALID_SSE_REG_MODE): Allow TFmode.
	(VALID_FP_MODE_P): Disallow TFmode.
	(VALID_INT_MODE_P): Allow TFmode in 64bit mode.
	* i386.md (TFmode patterns): Kill.
	(movtf, motf_rex64): New patterns.
Index: real.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/real.c,v
retrieving revision 1.129
diff -c -3 -p -r1.129 real.c
*** real.c	13 Oct 2003 21:16:18 -0000	1.129
--- real.c	30 Oct 2003 20:32:45 -0000
*************** encode_ieee_extended (const struct real_
*** 3030,3035 ****
--- 3030,3040 ----
      buf[0] = image_hi << 16, buf[1] = sig_hi, buf[2] = sig_lo;
    else
      buf[0] = sig_lo, buf[1] = sig_hi, buf[2] = image_hi;
+ 
+   /* Avoid uninitialized data to be output by compiler when XFmode is extended
+      to 128 bits.  */
+   if (GET_MODE_SIZE (XFmode) == 16)
+     buf[3] = 0;
  }
  
  static void
Index: reg-stack.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/reg-stack.c,v
retrieving revision 1.136
diff -c -3 -p -r1.136 reg-stack.c
*** reg-stack.c	25 Oct 2003 12:55:16 -0000	1.136
--- reg-stack.c	30 Oct 2003 20:32:45 -0000
*************** move_for_stack_reg (rtx insn, stack regs
*** 1124,1130 ****
  	  regstack->top--;
  	  CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (src));
  	}
!       else if ((GET_MODE (src) == XFmode || GET_MODE (src) == TFmode)
  	       && regstack->top < REG_STACK_SIZE - 1)
  	{
  	  /* A 387 cannot write an XFmode value to a MEM without
--- 1124,1130 ----
  	  regstack->top--;
  	  CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (src));
  	}
!       else if ((GET_MODE (src) == XFmode)
  	       && regstack->top < REG_STACK_SIZE - 1)
  	{
  	  /* A 387 cannot write an XFmode value to a MEM without
*************** move_for_stack_reg (rtx insn, stack regs
*** 1137,1146 ****
  	  rtx push_rtx, push_insn;
  	  rtx top_stack_reg = FP_MODE_REG (FIRST_STACK_REG, GET_MODE (src));
  
! 	  if (GET_MODE (src) == TFmode)
! 	    push_rtx = gen_movtf (top_stack_reg, top_stack_reg);
! 	  else
! 	    push_rtx = gen_movxf (top_stack_reg, top_stack_reg);
  	  push_insn = emit_insn_before (push_rtx, insn);
  	  REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_DEAD, top_stack_reg,
  						REG_NOTES (insn));
--- 1137,1143 ----
  	  rtx push_rtx, push_insn;
  	  rtx top_stack_reg = FP_MODE_REG (FIRST_STACK_REG, GET_MODE (src));
  
! 	  push_rtx = gen_movxf (top_stack_reg, top_stack_reg);
  	  push_insn = emit_insn_before (push_rtx, insn);
  	  REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_DEAD, top_stack_reg,
  						REG_NOTES (insn));
Index: config/i386/i386-modes.def
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386-modes.def,v
retrieving revision 1.4
diff -c -3 -p -r1.4 i386-modes.def
*** config/i386/i386-modes.def	13 Oct 2003 21:16:26 -0000	1.4
--- config/i386/i386-modes.def	30 Oct 2003 20:32:46 -0000
*************** along with GCC; see the file COPYING.  I
*** 18,28 ****
  the Free Software Foundation, 59 Temple Place - Suite 330,
  Boston, MA 02111-1307, USA.  */
  
! /* By default our XFmode is the 80-bit extended format.  If we use
!    TFmode instead, it's also the 80-bit format, but with padding. */
  
  FLOAT_MODE (XF, 12, ieee_extended_intel_96_format);
! FLOAT_MODE (TF, 16, ieee_extended_intel_128_format);
  
  /* Add any extra modes needed to represent the condition code.
  
--- 18,35 ----
  the Free Software Foundation, 59 Temple Place - Suite 330,
  Boston, MA 02111-1307, USA.  */
  
! /* x86_64 ABI specifies both XF and TF modes.
!    XFmode is __float80 is IEEE extended; TFmode is __float128
!    is IEEE quad.
! 
!    IEEE extended is 128 bits wide, except in ILP32 mode, but we
!    have to say it's 12 bytes so that the bitsize and wider_mode
!    tables are correctly set up.  We correct its size below.  */
  
  FLOAT_MODE (XF, 12, ieee_extended_intel_96_format);
! ADJUST_BYTESIZE  (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 12);
! ADJUST_ALIGNMENT (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 4);
! FLOAT_MODE (TF, 16, ieee_quad_format);
  
  /* Add any extra modes needed to represent the condition code.
  
Index: config/i386/i386.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.c,v
retrieving revision 1.613
diff -c -3 -p -r1.613 i386.c
*** config/i386/i386.c	27 Oct 2003 10:52:46 -0000	1.613
--- config/i386/i386.c	30 Oct 2003 20:32:46 -0000
*************** override_options (void)
*** 1370,1375 ****
--- 1370,1376 ----
    if (TARGET_SSE2)
      target_flags |= MASK_SSE;
  
+       target_flags |= (MASK_128BIT_LONG_DOUBLE);
    if (TARGET_64BIT)
      {
        if (TARGET_ALIGN_DOUBLE)
*************** classify_argument (enum machine_mode mod
*** 2178,2183 ****
--- 2179,2185 ----
        return 1;
      case CDImode:
      case TImode:
+     case TCmode:
        classes[0] = classes[1] = X86_64_INTEGER_CLASS;
        return 2;
      case CTImode:
*************** classify_argument (enum machine_mode mod
*** 2193,2203 ****
      case DFmode:
        classes[0] = X86_64_SSEDF_CLASS;
        return 1;
!     case TFmode:
        classes[0] = X86_64_X87_CLASS;
        classes[1] = X86_64_X87UP_CLASS;
        return 2;
!     case TCmode:
        classes[0] = X86_64_X87_CLASS;
        classes[1] = X86_64_X87UP_CLASS;
        classes[2] = X86_64_X87_CLASS;
--- 2195,2209 ----
      case DFmode:
        classes[0] = X86_64_SSEDF_CLASS;
        return 1;
!     case XFmode:
        classes[0] = X86_64_X87_CLASS;
        classes[1] = X86_64_X87UP_CLASS;
        return 2;
!     case TFmode:
!       classes[0] = X86_64_INTEGER_CLASS;
!       classes[1] = X86_64_INTEGER_CLASS;
!       return 2;
!     case XCmode:
        classes[0] = X86_64_X87_CLASS;
        classes[1] = X86_64_X87UP_CLASS;
        classes[2] = X86_64_X87_CLASS;
*************** construct_container (enum machine_mode m
*** 2334,2349 ****
      return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
    if (n == 2
        && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
!     return gen_rtx_REG (TFmode, FIRST_STACK_REG);
    if (n == 2 && class[0] == X86_64_INTEGER_CLASS
        && class[1] == X86_64_INTEGER_CLASS
!       && (mode == CDImode || mode == TImode)
        && intreg[0] + 1 == intreg[1])
      return gen_rtx_REG (mode, intreg[0]);
    if (n == 4
        && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS
        && class[2] == X86_64_X87_CLASS && class[3] == X86_64_X87UP_CLASS)
!     return gen_rtx_REG (TCmode, FIRST_STACK_REG);
  
    /* Otherwise figure out the entries of the PARALLEL.  */
    for (i = 0; i < n; i++)
--- 2340,2355 ----
      return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
    if (n == 2
        && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
!     return gen_rtx_REG (XFmode, FIRST_STACK_REG);
    if (n == 2 && class[0] == X86_64_INTEGER_CLASS
        && class[1] == X86_64_INTEGER_CLASS
!       && (mode == CDImode || mode == TImode || mode == TFmode)
        && intreg[0] + 1 == intreg[1])
      return gen_rtx_REG (mode, intreg[0]);
    if (n == 4
        && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS
        && class[2] == X86_64_X87_CLASS && class[3] == X86_64_X87UP_CLASS)
!     return gen_rtx_REG (XCmode, FIRST_STACK_REG);
  
    /* Otherwise figure out the entries of the PARALLEL.  */
    for (i = 0; i < n; i++)
*************** ix86_return_in_memory (tree type)
*** 2775,2782 ****
  	}
      }
  
!   if (mode == TFmode)
      return 0;
    if (size > 12)
      return 1;
    return 0;
--- 2781,2789 ----
  	}
      }
  
!   if (mode == TFmode || mode == XFmode)
      return 0;
+ 
    if (size > 12)
      return 1;
    return 0;
*************** ix86_libcall_value (enum machine_mode mo
*** 2791,2810 ****
      {
        switch (mode)
  	{
! 	  case SFmode:
! 	  case SCmode:
! 	  case DFmode:
! 	  case DCmode:
! 	    return gen_rtx_REG (mode, FIRST_SSE_REG);
! 	  case TFmode:
! 	  case TCmode:
! 	    return gen_rtx_REG (mode, FIRST_FLOAT_REG);
! 	  default:
! 	    return gen_rtx_REG (mode, 0);
  	}
      }
    else
!    return gen_rtx_REG (mode, ix86_value_regno (mode));
  }
  
  /* Given a mode, return the register to use for a return value.  */
--- 2798,2832 ----
      {
        switch (mode)
  	{
! 	case SFmode:
! 	case SCmode:
! 	case DFmode:
! 	case DCmode:
! 	  return gen_rtx_REG (mode, FIRST_SSE_REG);
! 	case XFmode:
! 	case XCmode:
! 	  return gen_rtx_REG (mode, FIRST_FLOAT_REG);
! 	case TFmode:
! 	  {
! 	    rtx ret = gen_rtx_PARALLEL (mode, rtvec_alloc (2));
! 	    XVECEXP (ret, 0, 0) = gen_rtx_EXPR_LIST
! 	       (VOIDmode,
! 		gen_rtx_REG (DImode, x86_64_int_parameter_registers [0]),
! 			     const0_rtx);
! 	    XVECEXP (ret, 0, 1) = gen_rtx_EXPR_LIST
! 	       (VOIDmode,
! 		gen_rtx_REG (DImode, x86_64_int_parameter_registers [1]),
! 			     GEN_INT (64));
! 	    return ret;
! 	  }
! 	case TCmode:
! 	  return NULL;
! 	default:
! 	  return gen_rtx_REG (mode, 0);
  	}
      }
    else
!     return gen_rtx_REG (mode, ix86_value_regno (mode));
  }
  
  /* Given a mode, return the register to use for a return value.  */
*************** init_ext_80387_constants (void)
*** 4253,4260 ****
        real_from_string (&ext_80387_constants_table[i], cst[i]);
        /* Ensure each constant is rounded to XFmode precision.  */
        real_convert (&ext_80387_constants_table[i],
! 		    TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode,
! 		    &ext_80387_constants_table[i]);
      }
  
    ext_80387_constants_init = 1;
--- 4275,4281 ----
        real_from_string (&ext_80387_constants_table[i], cst[i]);
        /* Ensure each constant is rounded to XFmode precision.  */
        real_convert (&ext_80387_constants_table[i],
! 		    XFmode, &ext_80387_constants_table[i]);
      }
  
    ext_80387_constants_init = 1;
*************** standard_80387_constant_p (rtx x)
*** 4276,4282 ****
  
    /* For XFmode constants, try to find a special 80387 instruction on
       those CPUs that benefit from them.  */
!   if ((GET_MODE (x) == XFmode || GET_MODE (x) == TFmode)
        && x86_ext_80387_constants & TUNEMASK)
      {
        REAL_VALUE_TYPE r;
--- 4297,4303 ----
  
    /* For XFmode constants, try to find a special 80387 instruction on
       those CPUs that benefit from them.  */
!   if (GET_MODE (x) == XFmode
        && x86_ext_80387_constants & TUNEMASK)
      {
        REAL_VALUE_TYPE r;
*************** standard_80387_constant_rtx (int idx)
*** 4347,4353 ****
      }
  
    return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
! 				       TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode);
  }
  
  /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
--- 4368,4374 ----
      }
  
    return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
! 				       XFmode);
  }
  
  /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
*************** print_operand (FILE *file, rtx x, int co
*** 7446,7452 ****
      }
  
    else if (GET_CODE (x) == CONST_DOUBLE
! 	   && (GET_MODE (x) == XFmode || GET_MODE (x) == TFmode))
      {
        char dstr[30];
  
--- 7467,7473 ----
      }
  
    else if (GET_CODE (x) == CONST_DOUBLE
! 	   && GET_MODE (x) == XFmode)
      {
        char dstr[30];
  
*************** ix86_prepare_fp_compare_args (enum rtx_c
*** 8686,8692 ****
    if (!is_sse
        && (fpcmp_mode == CCFPUmode
  	  || op_mode == XFmode
- 	  || op_mode == TFmode
  	  || ix86_use_fcomi_compare (code)))
      {
        op0 = force_reg (op_mode, op0);
--- 8707,8712 ----
*************** ix86_expand_branch (enum rtx_code code, 
*** 9161,9167 ****
      case SFmode:
      case DFmode:
      case XFmode:
-     case TFmode:
        {
  	rtvec vec;
  	int use_fcomi;
--- 9181,9186 ----
*************** ix86_split_to_parts (rtx operand, rtx *p
*** 10352,10358 ****
    int size;
  
    if (!TARGET_64BIT)
!     size = mode == TFmode ? 3 : (GET_MODE_SIZE (mode) / 4);
    else
      size = (GET_MODE_SIZE (mode) + 4) / 8;
  
--- 10371,10377 ----
    int size;
  
    if (!TARGET_64BIT)
!     size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
    else
      size = (GET_MODE_SIZE (mode) + 4) / 8;
  
*************** ix86_split_to_parts (rtx operand, rtx *p
*** 10412,10418 ****
  	      switch (mode)
  		{
  		case XFmode:
- 		case TFmode:
  		  REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
  		  parts[2] = gen_int_mode (l[2], SImode);
  		  break;
--- 10431,10436 ----
*************** ix86_split_to_parts (rtx operand, rtx *p
*** 10435,10452 ****
  	split_ti (&operand, 1, &parts[0], &parts[1]);
        if (mode == XFmode || mode == TFmode)
  	{
  	  if (REG_P (operand))
  	    {
  	      if (!reload_completed)
  		abort ();
  	      parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
! 	      parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
  	    }
  	  else if (offsettable_memref_p (operand))
  	    {
  	      operand = adjust_address (operand, DImode, 0);
  	      parts[0] = operand;
! 	      parts[1] = adjust_address (operand, SImode, 8);
  	    }
  	  else if (GET_CODE (operand) == CONST_DOUBLE)
  	    {
--- 10453,10471 ----
  	split_ti (&operand, 1, &parts[0], &parts[1]);
        if (mode == XFmode || mode == TFmode)
  	{
+ 	  enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
  	  if (REG_P (operand))
  	    {
  	      if (!reload_completed)
  		abort ();
  	      parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
! 	      parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
  	    }
  	  else if (offsettable_memref_p (operand))
  	    {
  	      operand = adjust_address (operand, DImode, 0);
  	      parts[0] = operand;
! 	      parts[1] = adjust_address (operand, upper_mode, 8);
  	    }
  	  else if (GET_CODE (operand) == CONST_DOUBLE)
  	    {
*************** ix86_split_to_parts (rtx operand, rtx *p
*** 10464,10470 ****
  		       DImode);
  	      else
  	        parts[0] = immed_double_const (l[0], l[1], DImode);
! 	      parts[1] = gen_int_mode (l[2], SImode);
  	    }
  	  else
  	    abort ();
--- 10483,10498 ----
  		       DImode);
  	      else
  	        parts[0] = immed_double_const (l[0], l[1], DImode);
! 	      if (upper_mode == SImode)
! 	        parts[1] = gen_int_mode (l[2], SImode);
! 	      else if (HOST_BITS_PER_WIDE_INT >= 64)
! 	        parts[1]
! 		  = gen_int_mode
! 		      ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
! 		       + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
! 		       DImode);
! 	      else
! 	        parts[1] = immed_double_const (l[2], l[3], DImode);
  	    }
  	  else
  	    abort ();
*************** ix86_split_long_move (rtx operands[])
*** 10585,10596 ****
  	{
  	  if (nparts == 3)
  	    {
! 	      /* We use only first 12 bytes of TFmode value, but for pushing we
! 		 are required to adjust stack as if we were pushing real 16byte
! 		 value.  */
! 	      if (mode == TFmode && !TARGET_64BIT)
! 		emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
! 				       GEN_INT (-4)));
  	      emit_move_insn (part[0][2], part[1][2]);
  	    }
  	}
--- 10613,10620 ----
  	{
  	  if (nparts == 3)
  	    {
! 	      if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
!                 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
  	      emit_move_insn (part[0][2], part[1][2]);
  	    }
  	}
*************** ix86_init_mmx_sse_builtins (void)
*** 13301,13306 ****
--- 13325,13351 ----
    tree v2di_ftype_v2di
      = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
  
+   tree float80_type;
+   tree float128_type;
+ 
+   /* The __float80 type.  */
+   if (TYPE_MODE (long_double_type_node) == XFmode)
+     (*lang_hooks.types.register_builtin_type) (long_double_type_node,
+ 					       "__float80");
+   else
+     {
+       /* The __float80 type.  */
+       float80_type = make_node (REAL_TYPE);
+       TYPE_PRECISION (float80_type) = 96;
+       layout_type (float80_type);
+       (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
+     }
+ 
+   float128_type = make_node (REAL_TYPE);
+   TYPE_PRECISION (float128_type) = 128;
+   layout_type (float128_type);
+   (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
+ 
    /* Add all builtins that are more or less simple operations on two
       operands.  */
    for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
*************** ix86_memory_move_cost (enum machine_mode
*** 14741,14747 ****
  	    index = 1;
  	    break;
  	  case XFmode:
- 	  case TFmode:
  	    index = 2;
  	    break;
  	  default:
--- 14786,14791 ----
Index: config/i386/i386.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.h,v
retrieving revision 1.355
diff -c -3 -p -r1.355 i386.h
*** config/i386/i386.h	20 Oct 2003 18:32:51 -0000	1.355
--- config/i386/i386.h	30 Oct 2003 20:32:46 -0000
*************** extern int x86_prefetch_sse;
*** 721,736 ****
  
  /* target machine storage layout */
  
! /* Define for XFmode or TFmode extended real floating point support.
!    The XFmode is specified by i386 ABI, while TFmode may be faster
!    due to alignment and simplifications in the address calculations.  */
! #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
! #define MAX_LONG_DOUBLE_TYPE_SIZE 128
! #ifdef __x86_64__
! #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
! #else
! #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
! #endif
  
  /* Set the value of FLT_EVAL_METHOD in float.h.  When using only the
     FPU, assume that the fpcw is set to extended precision; when using
--- 721,727 ----
  
  /* target machine storage layout */
  
! #define LONG_DOUBLE_TYPE_SIZE 96
  
  /* Set the value of FLT_EVAL_METHOD in float.h.  When using only the
     FPU, assume that the fpcw is set to extended precision; when using
*************** extern int x86_prefetch_sse;
*** 900,907 ****
  
  #define STACK_REGS
  #define IS_STACK_MODE(MODE)					\
!   ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode	\
!    || (MODE) == TFmode)
  
  /* Number of actual hardware registers.
     The hardware registers are assigned numbers for the compiler
--- 891,897 ----
  
  #define STACK_REGS
  #define IS_STACK_MODE(MODE)					\
!   ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode)	\
  
  /* Number of actual hardware registers.
     The hardware registers are assigned numbers for the compiler
*************** do {									\
*** 1049,1057 ****
  #define HARD_REGNO_NREGS(REGNO, MODE)   \
    (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO)	\
     ? (COMPLEX_MODE_P (MODE) ? 2 : 1)					\
!    : ((MODE) == TFmode							\
        ? (TARGET_64BIT ? 2 : 3)						\
!       : (MODE) == TCmode						\
        ? (TARGET_64BIT ? 4 : 6)						\
        : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
  
--- 1039,1047 ----
  #define HARD_REGNO_NREGS(REGNO, MODE)   \
    (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO)	\
     ? (COMPLEX_MODE_P (MODE) ? 2 : 1)					\
!    : ((MODE) == XFmode							\
        ? (TARGET_64BIT ? 2 : 3)						\
!       : (MODE) == XCmode						\
        ? (TARGET_64BIT ? 4 : 6)						\
        : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
  
*************** do {									\
*** 1061,1067 ****
  
  #define VALID_SSE_REG_MODE(MODE)					\
      ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode	\
!      || (MODE) == SFmode						\
       /* Always accept SSE2 modes so that xmmintrin.h compiles.  */	\
       || VALID_SSE2_REG_MODE (MODE)					\
       || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
--- 1051,1057 ----
  
  #define VALID_SSE_REG_MODE(MODE)					\
      ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode	\
!      || (MODE) == SFmode || (MODE) == TFmode				\
       /* Always accept SSE2 modes so that xmmintrin.h compiles.  */	\
       || VALID_SSE2_REG_MODE (MODE)					\
       || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
*************** do {									\
*** 1079,1099 ****
       : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
  
  #define VALID_FP_MODE_P(MODE)						\
!     ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode		\
!      || (!TARGET_64BIT && (MODE) == XFmode)				\
!      || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode	\
!      || (!TARGET_64BIT && (MODE) == XCmode))
  
  #define VALID_INT_MODE_P(MODE)						\
      ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode		\
       || (MODE) == DImode						\
       || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode	\
       || (MODE) == CDImode						\
!      || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
  
  /* Return true for modes passed in SSE registers.  */
  #define SSE_REG_MODE_P(MODE) \
!  ((MODE) == TImode || (MODE) == V16QImode				\
     || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode	\
     || (MODE) == V4SFmode || (MODE) == V4SImode)
  
--- 1069,1088 ----
       : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
  
  #define VALID_FP_MODE_P(MODE)						\
!     ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode		\
!      || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode)	\
  
  #define VALID_INT_MODE_P(MODE)						\
      ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode		\
       || (MODE) == DImode						\
       || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode	\
       || (MODE) == CDImode						\
!      || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode		\
!          || (MODE) == TFmode || (MODE) == TCmode)))
  
  /* Return true for modes passed in SSE registers.  */
  #define SSE_REG_MODE_P(MODE) \
!  ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode		\
     || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode	\
     || (MODE) == V4SFmode || (MODE) == V4SImode)
  
*************** enum reg_class
*** 1568,1582 ****
  /* Return the maximum number of consecutive registers
     needed to represent mode MODE in a register of class CLASS.  */
  /* On the 80386, this is the size of MODE in words,
!    except in the FP regs, where a single reg is always enough.
!    The TFmodes are really just 80bit values, so we use only 3 registers
!    to hold them, instead of 4, as the size would suggest.
!  */
  #define CLASS_MAX_NREGS(CLASS, MODE)					\
   (!MAYBE_INTEGER_CLASS_P (CLASS)					\
    ? (COMPLEX_MODE_P (MODE) ? 2 : 1)					\
!   : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE))		\
!      + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
  
  /* A C expression whose value is nonzero if pseudos that have been
     assigned to registers of class CLASS would likely be spilled
--- 1557,1568 ----
  /* Return the maximum number of consecutive registers
     needed to represent mode MODE in a register of class CLASS.  */
  /* On the 80386, this is the size of MODE in words,
!    except in the FP regs, where a single reg is always enough.  */
  #define CLASS_MAX_NREGS(CLASS, MODE)					\
   (!MAYBE_INTEGER_CLASS_P (CLASS)					\
    ? (COMPLEX_MODE_P (MODE) ? 2 : 1)					\
!   : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE)))			\
!       + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
  
  /* A C expression whose value is nonzero if pseudos that have been
     assigned to registers of class CLASS would likely be spilled
Index: config/i386/i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.489
diff -c -3 -p -r1.489 i386.md
*** config/i386/i386.md	27 Oct 2003 10:52:47 -0000	1.489
--- config/i386/i386.md	30 Oct 2003 20:32:46 -0000
***************
*** 716,732 ****
    [(set (reg:CC 17)
  	(compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
  		    (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
- {
-   ix86_compare_op0 = operands[0];
-   ix86_compare_op1 = operands[1];
-   DONE;
- })
- 
- (define_expand "cmptf"
-   [(set (reg:CC 17)
- 	(compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
- 		    (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
    "TARGET_80387"
  {
    ix86_compare_op0 = operands[0];
--- 716,721 ----
***************
*** 850,865 ****
  	(compare:CCFP
  	  (match_operand:XF 0 "register_operand" "f")
  	  (match_operand:XF 1 "register_operand" "f")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "* return output_fp_compare (insn, operands, 0, 0);"
-   [(set_attr "type" "fcmp")
-    (set_attr "mode" "XF")])
- 
- (define_insn "*cmpfp_2_tf"
-   [(set (reg:CCFP 18)
- 	(compare:CCFP
- 	  (match_operand:TF 0 "register_operand" "f")
- 	  (match_operand:TF 1 "register_operand" "f")))]
    "TARGET_80387"
    "* return output_fp_compare (insn, operands, 0, 0);"
    [(set_attr "type" "fcmp")
--- 839,844 ----
***************
*** 872,889 ****
  	     (match_operand:XF 1 "register_operand" "f")
  	     (match_operand:XF 2 "register_operand" "f"))]
  	  UNSPEC_FNSTSW))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "* return output_fp_compare (insn, operands, 2, 0);"
-   [(set_attr "type" "multi")
-    (set_attr "mode" "XF")])
- 
- (define_insn "*cmpfp_2_tf_1"
-   [(set (match_operand:HI 0 "register_operand" "=a")
- 	(unspec:HI
- 	  [(compare:CCFP
- 	     (match_operand:TF 1 "register_operand" "f")
- 	     (match_operand:TF 2 "register_operand" "f"))]
- 	  UNSPEC_FNSTSW))]
    "TARGET_80387"
    "* return output_fp_compare (insn, operands, 2, 0);"
    [(set_attr "type" "multi")
--- 851,856 ----
***************
*** 2744,2757 ****
  (define_expand "movxf"
    [(set (match_operand:XF 0 "nonimmediate_operand" "")
  	(match_operand:XF 1 "general_operand" ""))]
-   "!TARGET_128BIT_LONG_DOUBLE"
-   "ix86_expand_move (XFmode, operands); DONE;")
- 
- (define_expand "movtf"
-   [(set (match_operand:TF 0 "nonimmediate_operand" "")
- 	(match_operand:TF 1 "general_operand" ""))]
    ""
!   "ix86_expand_move (TFmode, operands); DONE;")
  
  ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
  ;; Size of pushdf using integer instructions is 3+3*memory operand size
--- 2711,2718 ----
  (define_expand "movxf"
    [(set (match_operand:XF 0 "nonimmediate_operand" "")
  	(match_operand:XF 1 "general_operand" ""))]
    ""
!   "ix86_expand_move (XFmode, operands); DONE;")
  
  ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
  ;; Size of pushdf using integer instructions is 3+3*memory operand size
***************
*** 2763,2779 ****
  (define_insn "*pushxf_nointeger"
    [(set (match_operand:XF 0 "push_operand" "=X,X,X")
  	(match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
-   "!TARGET_128BIT_LONG_DOUBLE && optimize_size"
- {
-   /* This insn should be already splitted before reg-stack.  */
-   abort ();
- }
-   [(set_attr "type" "multi")
-    (set_attr "mode" "XF,SI,SI")])
- 
- (define_insn "*pushtf_nointeger"
-   [(set (match_operand:TF 0 "push_operand" "=<,<,<")
- 	(match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
    "optimize_size"
  {
    /* This insn should be already splitted before reg-stack.  */
--- 2724,2729 ----
***************
*** 2785,2801 ****
  (define_insn "*pushxf_integer"
    [(set (match_operand:XF 0 "push_operand" "=<,<")
  	(match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
-   "!TARGET_128BIT_LONG_DOUBLE && !optimize_size"
- {
-   /* This insn should be already splitted before reg-stack.  */
-   abort ();
- }
-   [(set_attr "type" "multi")
-    (set_attr "mode" "XF,SI")])
- 
- (define_insn "*pushtf_integer"
-   [(set (match_operand:TF 0 "push_operand" "=<,<")
- 	(match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
    "!optimize_size"
  {
    /* This insn should be already splitted before reg-stack.  */
--- 2735,2740 ----
***************
*** 2809,2815 ****
  	(match_operand 1 "general_operand" ""))]
    "reload_completed
     && (GET_MODE (operands[0]) == XFmode
-        || GET_MODE (operands[0]) == TFmode
         || GET_MODE (operands[0]) == DFmode)
     && !ANY_FP_REG_P (operands[1])"
    [(const_int 0)]
--- 2748,2753 ----
***************
*** 2818,2847 ****
  (define_split
    [(set (match_operand:XF 0 "push_operand" "")
  	(match_operand:XF 1 "any_fp_register_operand" ""))]
-   "!TARGET_128BIT_LONG_DOUBLE"
-   [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
-    (set (mem:XF (reg:SI 7)) (match_dup 1))])
- 
- (define_split
-   [(set (match_operand:TF 0 "push_operand" "")
- 	(match_operand:TF 1 "any_fp_register_operand" ""))]
    "!TARGET_64BIT"
!   [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
!    (set (mem:TF (reg:SI 7)) (match_dup 1))])
  
  (define_split
!   [(set (match_operand:TF 0 "push_operand" "")
! 	(match_operand:TF 1 "any_fp_register_operand" ""))]
    "TARGET_64BIT"
!   [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
!    (set (mem:TF (reg:DI 7)) (match_dup 1))])
  
  ;; Do not use integer registers when optimizing for size
  (define_insn "*movxf_nointeger"
    [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
  	(match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
!   "!TARGET_128BIT_LONG_DOUBLE
!    && optimize_size
     && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
     && (reload_in_progress || reload_completed
         || GET_CODE (operands[1]) != CONST_DOUBLE
--- 2756,2779 ----
  (define_split
    [(set (match_operand:XF 0 "push_operand" "")
  	(match_operand:XF 1 "any_fp_register_operand" ""))]
    "!TARGET_64BIT"
!   [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
!    (set (mem:XF (reg:SI 7)) (match_dup 1))]
!   "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
  
  (define_split
!   [(set (match_operand:XF 0 "push_operand" "")
! 	(match_operand:XF 1 "any_fp_register_operand" ""))]
    "TARGET_64BIT"
!   [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
!    (set (mem:XF (reg:DI 7)) (match_dup 1))]
!   "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
  
  ;; Do not use integer registers when optimizing for size
  (define_insn "*movxf_nointeger"
    [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
  	(match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
!   "optimize_size
     && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
     && (reload_in_progress || reload_completed
         || GET_CODE (operands[1]) != CONST_DOUBLE
***************
*** 2882,2937 ****
    [(set_attr "type" "fmov,fmov,fmov,multi,multi")
     (set_attr "mode" "XF,XF,XF,SI,SI")])
  
- (define_insn "*movtf_nointeger"
-   [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
- 	(match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
-   "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-    && optimize_size
-    && (reload_in_progress || reload_completed
-        || GET_CODE (operands[1]) != CONST_DOUBLE
-        || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
-        || memory_operand (operands[0], TFmode))" 
- {
-   switch (which_alternative)
-     {
-     case 0:
-       if (REG_P (operands[1])
-           && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- 	{
- 	  if (REGNO (operands[0]) == FIRST_STACK_REG
- 	      && TARGET_USE_FFREEP)
- 	    return "ffreep\t%y0";
-           return "fstp\t%y0";
- 	}
-       else if (STACK_TOP_P (operands[0]))
-         return "fld%z1\t%y1";
-       else
-         return "fst\t%y0";
- 
-     case 1:
-       /* There is no non-popping store to memory for XFmode.  So if
- 	 we need one, follow the store with a load.  */
-       if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-         return "fstp%z0\t%y0\;fld%z0\t%y0";
-       else
-         return "fstp%z0\t%y0";
- 
-     case 2:
-       return standard_80387_constant_opcode (operands[1]);
- 
-     case 3: case 4:
-       return "#";
-     }
-   abort();
- }
-   [(set_attr "type" "fmov,fmov,fmov,multi,multi")
-    (set_attr "mode" "XF,XF,XF,SI,SI")])
- 
  (define_insn "*movxf_integer"
    [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
  	(match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
!   "!TARGET_128BIT_LONG_DOUBLE
!    && !optimize_size
     && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
     && (reload_in_progress || reload_completed
         || GET_CODE (operands[1]) != CONST_DOUBLE
--- 2814,2823 ----
    [(set_attr "type" "fmov,fmov,fmov,multi,multi")
     (set_attr "mode" "XF,XF,XF,SI,SI")])
  
  (define_insn "*movxf_integer"
    [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
  	(match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
!   "!optimize_size
     && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
     && (reload_in_progress || reload_completed
         || GET_CODE (operands[1]) != CONST_DOUBLE
***************
*** 2972,3028 ****
    [(set_attr "type" "fmov,fmov,fmov,multi,multi")
     (set_attr "mode" "XF,XF,XF,SI,SI")])
  
- (define_insn "*movtf_integer"
-   [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
- 	(match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
-   "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-    && !optimize_size
-    && (reload_in_progress || reload_completed
-        || GET_CODE (operands[1]) != CONST_DOUBLE
-        || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
-        || memory_operand (operands[0], TFmode))" 
- {
-   switch (which_alternative)
-     {
-     case 0:
-       if (REG_P (operands[1])
-           && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- 	{
- 	  if (REGNO (operands[0]) == FIRST_STACK_REG
- 	      && TARGET_USE_FFREEP)
- 	    return "ffreep\t%y0";
-           return "fstp\t%y0";
- 	}
-       else if (STACK_TOP_P (operands[0]))
-         return "fld%z1\t%y1";
-       else
-         return "fst\t%y0";
- 
-     case 1:
-       /* There is no non-popping store to memory for XFmode.  So if
- 	 we need one, follow the store with a load.  */
-       if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-         return "fstp%z0\t%y0\;fld%z0\t%y0";
-       else
-         return "fstp%z0\t%y0";
- 
-     case 2:
-       return standard_80387_constant_opcode (operands[1]);
- 
-     case 3: case 4:
-       return "#";
-     }
-   abort();
- }
-   [(set_attr "type" "fmov,fmov,fmov,multi,multi")
-    (set_attr "mode" "XF,XF,XF,SI,SI")])
- 
  (define_split
    [(set (match_operand 0 "nonimmediate_operand" "")
  	(match_operand 1 "general_operand" ""))]
    "reload_completed
     && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
!    && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
     && ! (ANY_FP_REG_P (operands[0]) || 
  	 (GET_CODE (operands[0]) == SUBREG
  	  && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
--- 2858,2869 ----
    [(set_attr "type" "fmov,fmov,fmov,multi,multi")
     (set_attr "mode" "XF,XF,XF,SI,SI")])
  
  (define_split
    [(set (match_operand 0 "nonimmediate_operand" "")
  	(match_operand 1 "general_operand" ""))]
    "reload_completed
     && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
!    && GET_MODE (operands[0]) == XFmode
     && ! (ANY_FP_REG_P (operands[0]) || 
  	 (GET_CODE (operands[0]) == SUBREG
  	  && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
***************
*** 3037,3043 ****
  	(match_operand 1 "memory_operand" ""))]
    "reload_completed
     && GET_CODE (operands[1]) == MEM
!    && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
         || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
     && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
     && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
--- 2878,2884 ----
  	(match_operand 1 "memory_operand" ""))]
    "reload_completed
     && GET_CODE (operands[1]) == MEM
!    && (GET_MODE (operands[0]) == XFmode
         || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
     && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
     && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
***************
*** 3067,3087 ****
  }
    [(set_attr "type" "fxch")
     (set_attr "mode" "XF")])
- 
- (define_insn "swaptf"
-   [(set (match_operand:TF 0 "register_operand" "+f")
- 	(match_operand:TF 1 "register_operand" "+f"))
-    (set (match_dup 1)
- 	(match_dup 0))]
-   ""
- {
-   if (STACK_TOP_P (operands[0]))
-     return "fxch\t%1";
-   else
-     return "fxch\t%0";
- }
-   [(set_attr "type" "fxch")
-    (set_attr "mode" "XF")])
  
  ;; Zero extension instructions
  
--- 2908,2913 ----
***************
*** 3632,3693 ****
  (define_split
    [(set (match_operand:XF 0 "push_operand" "")
  	(float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
!   "!TARGET_128BIT_LONG_DOUBLE"
!   [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
!    (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
! 
! (define_insn "*dummy_extendsftf2"
!   [(set (match_operand:TF 0 "push_operand" "=<")
! 	(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
!   "0"
!   "#")
! 
! (define_split
!   [(set (match_operand:TF 0 "push_operand" "")
! 	(float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
!   "!TARGET_64BIT"
!   [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
!    (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
  
  (define_split
!   [(set (match_operand:TF 0 "push_operand" "")
! 	(float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
    "TARGET_64BIT"
!   [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
!    (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
! 
! (define_insn "*dummy_extenddfxf2"
!   [(set (match_operand:XF 0 "push_operand" "=<")
! 	(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
!   "0"
!   "#")
  
  (define_split
    [(set (match_operand:XF 0 "push_operand" "")
  	(float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
!   "!TARGET_128BIT_LONG_DOUBLE"
!   [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
!    (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
! 
! (define_insn "*dummy_extenddftf2"
!   [(set (match_operand:TF 0 "push_operand" "=<")
! 	(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
!   "0"
!   "#")
! 
! (define_split
!   [(set (match_operand:TF 0 "push_operand" "")
! 	(float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
!   "!TARGET_64BIT"
!   [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
!    (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
  
  (define_split
!   [(set (match_operand:TF 0 "push_operand" "")
! 	(float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
    "TARGET_64BIT"
!   [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
!    (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
  
  (define_expand "extendsfdf2"
    [(set (match_operand:DF 0 "nonimmediate_operand" "")
--- 3458,3491 ----
  (define_split
    [(set (match_operand:XF 0 "push_operand" "")
  	(float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
!   ""
!   [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
!    (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))]
!   "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
  
  (define_split
!   [(set (match_operand:XF 0 "push_operand" "")
! 	(float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
    "TARGET_64BIT"
!   [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
!    (set (mem:DF (reg:DI 7)) (float_extend:XF (match_dup 1)))]
!   "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
  
  (define_split
    [(set (match_operand:XF 0 "push_operand" "")
  	(float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
!   ""
!   [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
!    (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))]
!   "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
  
  (define_split
!   [(set (match_operand:XF 0 "push_operand" "")
! 	(float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
    "TARGET_64BIT"
!   [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
!    (set (mem:XF (reg:DI 7)) (float_extend:XF (match_dup 1)))]
!   "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
  
  (define_expand "extendsfdf2"
    [(set (match_operand:DF 0 "nonimmediate_operand" "")
***************
*** 3747,3753 ****
  (define_expand "extendsfxf2"
    [(set (match_operand:XF 0 "nonimmediate_operand" "")
          (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
  {
    /* ??? Needed for compress_float_constant since all fp constants
       are LEGITIMATE_CONSTANT_P.  */
--- 3545,3551 ----
  (define_expand "extendsfxf2"
    [(set (match_operand:XF 0 "nonimmediate_operand" "")
          (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
!   "TARGET_80387"
  {
    /* ??? Needed for compress_float_constant since all fp constants
       are LEGITIMATE_CONSTANT_P.  */
***************
*** 3760,3810 ****
  (define_insn "*extendsfxf2_1"
    [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
          (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
-    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- {
-   switch (which_alternative)
-     {
-     case 0:
-       if (REG_P (operands[1])
-           && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-         return "fstp\t%y0";
-       else if (STACK_TOP_P (operands[0]))
-         return "fld%z1\t%y1";
-       else
-         return "fst\t%y0";
- 
-     case 1:
-       /* There is no non-popping store to memory for XFmode.  So if
- 	 we need one, follow the store with a load.  */
-       if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-         return "fstp%z0\t%y0\n\tfld%z0\t%y0";
-       else
-         return "fstp%z0\t%y0";
- 
-     default:
-       abort ();
-     }
- }
-   [(set_attr "type" "fmov")
-    (set_attr "mode" "SF,XF")])
- 
- (define_expand "extendsftf2"
-   [(set (match_operand:TF 0 "nonimmediate_operand" "")
-         (float_extend:TF (match_operand:SF 1 "general_operand" "")))]
-   "TARGET_80387"
- {
-   /* ??? Needed for compress_float_constant since all fp constants
-      are LEGITIMATE_CONSTANT_P.  */
-   if (GET_CODE (operands[1]) == CONST_DOUBLE)
-     operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
-   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-     operands[1] = force_reg (SFmode, operands[1]);
- })
- 
- (define_insn "*extendsftf2_1"
-   [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
-         (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
    "TARGET_80387
     && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
  {
--- 3558,3563 ----
***************
*** 3837,3843 ****
  (define_expand "extenddfxf2"
    [(set (match_operand:XF 0 "nonimmediate_operand" "")
          (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
  {
    /* ??? Needed for compress_float_constant since all fp constants
       are LEGITIMATE_CONSTANT_P.  */
--- 3590,3596 ----
  (define_expand "extenddfxf2"
    [(set (match_operand:XF 0 "nonimmediate_operand" "")
          (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
!   "TARGET_80387"
  {
    /* ??? Needed for compress_float_constant since all fp constants
       are LEGITIMATE_CONSTANT_P.  */
***************
*** 3850,3900 ****
  (define_insn "*extenddfxf2_1"
    [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
          (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
-    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- {
-   switch (which_alternative)
-     {
-     case 0:
-       if (REG_P (operands[1])
-           && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-         return "fstp\t%y0";
-       else if (STACK_TOP_P (operands[0]))
-         return "fld%z1\t%y1";
-       else
-         return "fst\t%y0";
- 
-     case 1:
-       /* There is no non-popping store to memory for XFmode.  So if
- 	 we need one, follow the store with a load.  */
-       if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-         return "fstp%z0\t%y0\n\tfld%z0\t%y0";
-       else
-         return "fstp%z0\t%y0";
- 
-     default:
-       abort ();
-     }
- }
-   [(set_attr "type" "fmov")
-    (set_attr "mode" "DF,XF")])
- 
- (define_expand "extenddftf2"
-   [(set (match_operand:TF 0 "nonimmediate_operand" "")
-         (float_extend:TF (match_operand:DF 1 "general_operand" "")))]
-   "TARGET_80387"
- {
-   /* ??? Needed for compress_float_constant since all fp constants
-      are LEGITIMATE_CONSTANT_P.  */
-   if (GET_CODE (operands[1]) == CONST_DOUBLE)
-     operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
-   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-     operands[1] = force_reg (DFmode, operands[1]);
- })
- 
- (define_insn "*extenddftf2_1"
-   [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
-         (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
    "TARGET_80387
     && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
  {
--- 3603,3608 ----
***************
*** 4169,4175 ****
  		   (float_truncate:SF
  		    (match_operand:XF 1 "register_operand" "")))
  	      (clobber (match_dup 2))])]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
    "operands[2] = assign_386_stack_local (SFmode, 0);")
  
  (define_insn "*truncxfsf2_1"
--- 3877,3883 ----
  		   (float_truncate:SF
  		    (match_operand:XF 1 "register_operand" "")))
  	      (clobber (match_dup 2))])]
!   "TARGET_80387"
    "operands[2] = assign_386_stack_local (SFmode, 0);")
  
  (define_insn "*truncxfsf2_1"
***************
*** 4177,4183 ****
  	(float_truncate:SF
  	 (match_operand:XF 1 "register_operand" "f,f,f,f")))
     (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
  {
    switch (which_alternative)
      {
--- 3885,3891 ----
  	(float_truncate:SF
  	 (match_operand:XF 1 "register_operand" "f,f,f,f")))
     (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
!   "TARGET_80387"
  {
    switch (which_alternative)
      {
***************
*** 4197,4203 ****
    [(set (match_operand:SF 0 "memory_operand" "=m")
  	(float_truncate:SF
  	 (match_operand:XF 1 "register_operand" "f")))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
  {
    if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
      return "fstp%z0\t%y0";
--- 3905,3911 ----
    [(set (match_operand:SF 0 "memory_operand" "=m")
  	(float_truncate:SF
  	 (match_operand:XF 1 "register_operand" "f")))]
!   "TARGET_80387"
  {
    if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
      return "fstp%z0\t%y0";
***************
*** 4226,4300 ****
     (set (match_dup 0) (match_dup 2))]
    "")
  
- (define_expand "trunctfsf2"
-   [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
- 		   (float_truncate:SF
- 		    (match_operand:TF 1 "register_operand" "")))
- 	      (clobber (match_dup 2))])]
-   "TARGET_80387"
-   "operands[2] = assign_386_stack_local (SFmode, 0);")
- 
- (define_insn "*trunctfsf2_1"
-   [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
- 	(float_truncate:SF
- 	 (match_operand:TF 1 "register_operand" "f,f,f,f")))
-    (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
-   "TARGET_80387"
- {
-   switch (which_alternative)
-     {
-     case 0:
-       if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- 	return "fstp%z0\t%y0";
-       else
- 	return "fst%z0\t%y0";
-     default:
-       abort();
-     }
- }
-   [(set_attr "type" "fmov,multi,multi,multi")
-    (set_attr "mode" "SF")])
- 
- (define_insn "*trunctfsf2_2"
-   [(set (match_operand:SF 0 "memory_operand" "=m")
- 	(float_truncate:SF
- 	 (match_operand:TF 1 "register_operand" "f")))]
-   "TARGET_80387"
- {
-   if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-     return "fstp%z0\t%y0";
-   else
-     return "fst%z0\t%y0";
- }
-   [(set_attr "type" "fmov")
-    (set_attr "mode" "SF")])
- 
- (define_split
-   [(set (match_operand:SF 0 "memory_operand" "")
- 	(float_truncate:SF
- 	 (match_operand:TF 1 "register_operand" "")))
-    (clobber (match_operand:SF 2 "memory_operand" ""))]
-   "TARGET_80387"
-   [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
-   "")
- 
- (define_split
-   [(set (match_operand:SF 0 "register_operand" "")
- 	(float_truncate:SF
- 	 (match_operand:TF 1 "register_operand" "")))
-    (clobber (match_operand:SF 2 "memory_operand" ""))]
-   "TARGET_80387 && reload_completed"
-   [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
-    (set (match_dup 0) (match_dup 2))]
-   "")
- 
- 
  (define_expand "truncxfdf2"
    [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
  		   (float_truncate:DF
  		    (match_operand:XF 1 "register_operand" "")))
  	      (clobber (match_dup 2))])]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
    "operands[2] = assign_386_stack_local (DFmode, 0);")
  
  (define_insn "*truncxfdf2_1"
--- 3934,3945 ----
     (set (match_dup 0) (match_dup 2))]
    "")
  
  (define_expand "truncxfdf2"
    [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
  		   (float_truncate:DF
  		    (match_operand:XF 1 "register_operand" "")))
  	      (clobber (match_dup 2))])]
!   "TARGET_80387"
    "operands[2] = assign_386_stack_local (DFmode, 0);")
  
  (define_insn "*truncxfdf2_1"
***************
*** 4302,4308 ****
  	(float_truncate:DF
  	 (match_operand:XF 1 "register_operand" "f,f,f,f")))
     (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
  {
    switch (which_alternative)
      {
--- 3947,3953 ----
  	(float_truncate:DF
  	 (match_operand:XF 1 "register_operand" "f,f,f,f")))
     (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
!   "TARGET_80387"
  {
    switch (which_alternative)
      {
***************
*** 4323,4329 ****
    [(set (match_operand:DF 0 "memory_operand" "=m")
  	(float_truncate:DF
  	  (match_operand:XF 1 "register_operand" "f")))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
  {
    if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
      return "fstp%z0\t%y0";
--- 3968,3974 ----
    [(set (match_operand:DF 0 "memory_operand" "=m")
  	(float_truncate:DF
  	  (match_operand:XF 1 "register_operand" "f")))]
!   "TARGET_80387"
  {
    if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
      return "fstp%z0\t%y0";
***************
*** 4352,4420 ****
     (set (match_dup 0) (match_dup 2))]
    "")
  
- (define_expand "trunctfdf2"
-   [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
- 		   (float_truncate:DF
- 		    (match_operand:TF 1 "register_operand" "")))
- 	      (clobber (match_dup 2))])]
-   "TARGET_80387"
-   "operands[2] = assign_386_stack_local (DFmode, 0);")
- 
- (define_insn "*trunctfdf2_1"
-   [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
- 	(float_truncate:DF
- 	 (match_operand:TF 1 "register_operand" "f,f,f,f")))
-    (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
-   "TARGET_80387"
- {
-   switch (which_alternative)
-     {
-     case 0:
-       if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- 	return "fstp%z0\t%y0";
-       else
- 	return "fst%z0\t%y0";
-     default:
-       abort();
-     }
-   abort ();
- }
-   [(set_attr "type" "fmov,multi,multi,multi")
-    (set_attr "mode" "DF")])
- 
- 	(define_insn "*trunctfdf2_2"
-   [(set (match_operand:DF 0 "memory_operand" "=m")
- 	(float_truncate:DF
- 	  (match_operand:TF 1 "register_operand" "f")))]
-   "TARGET_80387"
- {
-   if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-     return "fstp%z0\t%y0";
-   else
-     return "fst%z0\t%y0";
- }
-   [(set_attr "type" "fmov")
-    (set_attr "mode" "DF")])
- 
- (define_split
-   [(set (match_operand:DF 0 "memory_operand" "")
- 	(float_truncate:DF
- 	 (match_operand:TF 1 "register_operand" "")))
-    (clobber (match_operand:DF 2 "memory_operand" ""))]
-   "TARGET_80387"
-   [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
-   "")
- 
- (define_split
-   [(set (match_operand:DF 0 "register_operand" "")
- 	(float_truncate:DF
- 	 (match_operand:TF 1 "register_operand" "")))
-    (clobber (match_operand:DF 2 "memory_operand" ""))]
-   "TARGET_80387 && reload_completed"
-   [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
-    (set (match_dup 0) (match_dup 2))]
-   "")
- 
  
  ;; %%% Break up all these bad boys.
  
--- 3997,4002 ----
***************
*** 4423,4434 ****
  (define_expand "fix_truncxfdi2"
    [(set (match_operand:DI 0 "nonimmediate_operand" "")
          (fix:DI (match_operand:XF 1 "register_operand" "")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "")
- 
- (define_expand "fix_trunctfdi2"
-   [(set (match_operand:DI 0 "nonimmediate_operand" "")
- 	(fix:DI (match_operand:TF 1 "register_operand" "")))]
    "TARGET_80387"
    "")
  
--- 4005,4010 ----
***************
*** 4590,4601 ****
  (define_expand "fix_truncxfsi2"
    [(set (match_operand:SI 0 "nonimmediate_operand" "")
  	(fix:SI (match_operand:XF 1 "register_operand" "")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "")
- 
- (define_expand "fix_trunctfsi2"
-   [(set (match_operand:SI 0 "nonimmediate_operand" "")
- 	(fix:SI (match_operand:TF 1 "register_operand" "")))]
    "TARGET_80387"
    "")
  
--- 4166,4171 ----
***************
*** 4751,4762 ****
  (define_expand "fix_truncxfhi2"
    [(set (match_operand:HI 0 "nonimmediate_operand" "")
          (fix:HI (match_operand:XF 1 "register_operand" "")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "")
- 
- (define_expand "fix_trunctfhi2"
-   [(set (match_operand:HI 0 "nonimmediate_operand" "")
- 	(fix:HI (match_operand:TF 1 "register_operand" "")))]
    "TARGET_80387"
    "")
  
--- 4321,4326 ----
***************
*** 5103,5119 ****
  (define_insn "floathixf2"
    [(set (match_operand:XF 0 "register_operand" "=f,f")
  	(float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "@
-    fild%z1\t%1
-    #"
-   [(set_attr "type" "fmov,multi")
-    (set_attr "mode" "XF")
-    (set_attr "fp_int_src" "true")])
- 
- (define_insn "floathitf2"
-   [(set (match_operand:TF 0 "register_operand" "=f,f")
- 	(float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
    "TARGET_80387"
    "@
     fild%z1\t%1
--- 4667,4672 ----
***************
*** 5125,5141 ****
  (define_insn "floatsixf2"
    [(set (match_operand:XF 0 "register_operand" "=f,f")
  	(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "@
-    fild%z1\t%1
-    #"
-   [(set_attr "type" "fmov,multi")
-    (set_attr "mode" "XF")
-    (set_attr "fp_int_src" "true")])
- 
- (define_insn "floatsitf2"
-   [(set (match_operand:TF 0 "register_operand" "=f,f")
- 	(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
    "TARGET_80387"
    "@
     fild%z1\t%1
--- 4678,4683 ----
***************
*** 5147,5163 ****
  (define_insn "floatdixf2"
    [(set (match_operand:XF 0 "register_operand" "=f,f")
  	(float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "@
-    fild%z1\t%1
-    #"
-   [(set_attr "type" "fmov,multi")
-    (set_attr "mode" "XF")
-    (set_attr "fp_int_src" "true")])
- 
- (define_insn "floatditf2"
-   [(set (match_operand:TF 0 "register_operand" "=f,f")
- 	(float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
    "TARGET_80387"
    "@
     fild%z1\t%1
--- 4689,4694 ----
***************
*** 6858,6870 ****
    [(set (match_operand:XF 0 "register_operand" "")
  	(plus:XF (match_operand:XF 1 "register_operand" "")
  		 (match_operand:XF 2 "register_operand" "")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "")
- 
- (define_expand "addtf3"
-   [(set (match_operand:TF 0 "register_operand" "")
- 	(plus:TF (match_operand:TF 1 "register_operand" "")
- 		 (match_operand:TF 2 "register_operand" "")))]
    "TARGET_80387"
    "")
  
--- 6389,6394 ----
***************
*** 7211,7223 ****
    [(set (match_operand:XF 0 "register_operand" "")
  	(minus:XF (match_operand:XF 1 "register_operand" "")
  		  (match_operand:XF 2 "register_operand" "")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "")
- 
- (define_expand "subtf3"
-   [(set (match_operand:TF 0 "register_operand" "")
- 	(minus:TF (match_operand:TF 1 "register_operand" "")
- 		  (match_operand:TF 2 "register_operand" "")))]
    "TARGET_80387"
    "")
  
--- 6735,6740 ----
***************
*** 7729,7741 ****
    [(set (match_operand:XF 0 "register_operand" "")
  	(mult:XF (match_operand:XF 1 "register_operand" "")
  		 (match_operand:XF 2 "register_operand" "")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "")
- 
- (define_expand "multf3"
-   [(set (match_operand:TF 0 "register_operand" "")
- 	(mult:TF (match_operand:TF 1 "register_operand" "")
- 		 (match_operand:TF 2 "register_operand" "")))]
    "TARGET_80387"
    "")
  
--- 7246,7251 ----
***************
*** 7783,7795 ****
    [(set (match_operand:XF 0 "register_operand" "")
  	(div:XF (match_operand:XF 1 "register_operand" "")
  		(match_operand:XF 2 "register_operand" "")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "")
- 
- (define_expand "divtf3"
-   [(set (match_operand:TF 0 "register_operand" "")
- 	(div:TF (match_operand:TF 1 "register_operand" "")
- 		(match_operand:TF 2 "register_operand" "")))]
    "TARGET_80387"
    "")
  
--- 7293,7298 ----
***************
*** 10018,10025 ****
  {
    int size = GET_MODE_SIZE (GET_MODE (operands[1]));
  
!   /* XFmode's size is 12, TFmode 16, but only 10 bytes are used.  */
!   if (size >= 12)
      size = 10;
    operands[0] = adjust_address (operands[0], QImode, size - 1);
    operands[1] = gen_int_mode (0x80, QImode);
--- 9521,9527 ----
  {
    int size = GET_MODE_SIZE (GET_MODE (operands[1]));
  
!   if (GET_MODE (operands[1]) == XFmode)
      size = 10;
    operands[0] = adjust_address (operands[0], QImode, size - 1);
    operands[1] = gen_int_mode (0x80, QImode);
***************
*** 10196,10210 ****
    [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
  		   (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
  	      (clobber (reg:CC 17))])]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
- 
- (define_expand "negtf2"
-   [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
- 		   (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
- 	      (clobber (reg:CC 17))])]
    "TARGET_80387"
!   "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
  
  ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
  ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
--- 9698,9705 ----
    [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
  		   (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
  	      (clobber (reg:CC 17))])]
    "TARGET_80387"
!   "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
  
  ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
  ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
***************
*** 10213,10219 ****
    [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
  	(neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
     (clobber (reg:CC 17))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
     && ix86_unary_operator_ok (NEG, XFmode, operands)"
    "#")
  
--- 9708,9714 ----
    [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
  	(neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
     (clobber (reg:CC 17))]
!   "TARGET_80387
     && ix86_unary_operator_ok (NEG, XFmode, operands)"
    "#")
  
***************
*** 10237,10272 ****
     operands[0] = gen_rtx_REG (SImode,
  			      true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
  
- ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
- ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
- ;; to itself.
- (define_insn "*negtf2_if"
-   [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
- 	(neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
-    (clobber (reg:CC 17))]
-   "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
-   "#")
- 
- (define_split
-   [(set (match_operand:TF 0 "fp_register_operand" "")
- 	(neg:TF (match_operand:TF 1 "register_operand" "")))
-    (clobber (reg:CC 17))]
-   "TARGET_80387 && reload_completed"
-   [(set (match_dup 0)
- 	(neg:TF (match_dup 1)))]
-   "")
- 
- (define_split
-   [(set (match_operand:TF 0 "register_and_not_fp_reg_operand" "")
- 	(neg:TF (match_operand:TF 1 "register_operand" "")))
-    (clobber (reg:CC 17))]
-   "TARGET_80387 && reload_completed"
-   [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
- 	      (clobber (reg:CC 17))])]
-   "operands[1] = GEN_INT (0x8000);
-    operands[0] = gen_rtx_REG (SImode,
- 			      true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
- 
  ;; Conditionalize these after reload. If they matches before reload, we 
  ;; lose the clobber and ability to use integer instructions.
  
--- 9732,9737 ----
***************
*** 10301,10307 ****
  (define_insn "*negxf2_1"
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(neg:XF (match_operand:XF 1 "register_operand" "0")))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && reload_completed"
    "fchs"
    [(set_attr "type" "fsgn")
     (set_attr "mode" "XF")
--- 9766,9772 ----
  (define_insn "*negxf2_1"
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(neg:XF (match_operand:XF 1 "register_operand" "0")))]
!   "TARGET_80387 && reload_completed"
    "fchs"
    [(set_attr "type" "fsgn")
     (set_attr "mode" "XF")
***************
*** 10311,10317 ****
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(neg:XF (float_extend:XF
  		  (match_operand:DF 1 "register_operand" "0"))))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
    "fchs"
    [(set_attr "type" "fsgn")
     (set_attr "mode" "XF")
--- 9776,9782 ----
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(neg:XF (float_extend:XF
  		  (match_operand:DF 1 "register_operand" "0"))))]
!   "TARGET_80387"
    "fchs"
    [(set_attr "type" "fsgn")
     (set_attr "mode" "XF")
***************
*** 10321,10355 ****
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(neg:XF (float_extend:XF
  		  (match_operand:SF 1 "register_operand" "0"))))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "fchs"
-   [(set_attr "type" "fsgn")
-    (set_attr "mode" "XF")
-    (set_attr "ppro_uops" "few")])
- 
- (define_insn "*negtf2_1"
-   [(set (match_operand:TF 0 "register_operand" "=f")
- 	(neg:TF (match_operand:TF 1 "register_operand" "0")))]
-   "TARGET_80387 && reload_completed"
-   "fchs"
-   [(set_attr "type" "fsgn")
-    (set_attr "mode" "XF")
-    (set_attr "ppro_uops" "few")])
- 
- (define_insn "*negextenddftf2"
-   [(set (match_operand:TF 0 "register_operand" "=f")
- 	(neg:TF (float_extend:TF
- 		  (match_operand:DF 1 "register_operand" "0"))))]
-   "TARGET_80387"
-   "fchs"
-   [(set_attr "type" "fsgn")
-    (set_attr "mode" "XF")
-    (set_attr "ppro_uops" "few")])
- 
- (define_insn "*negextendsftf2"
-   [(set (match_operand:TF 0 "register_operand" "=f")
- 	(neg:TF (float_extend:TF
- 		  (match_operand:SF 1 "register_operand" "0"))))]
    "TARGET_80387"
    "fchs"
    [(set_attr "type" "fsgn")
--- 9786,9791 ----
***************
*** 10491,10498 ****
  {
    int size = GET_MODE_SIZE (GET_MODE (operands[1]));
  
!   /* XFmode's size is 12, TFmode 16, but only 10 bytes are used.  */
!   if (size >= 12)
      size = 10;
    operands[0] = adjust_address (operands[0], QImode, size - 1);
    operands[1] = gen_int_mode (~0x80, QImode);
--- 9927,9933 ----
  {
    int size = GET_MODE_SIZE (GET_MODE (operands[1]));
  
!   if (GET_MODE (operands[1]) == XFmode)
      size = 10;
    operands[0] = adjust_address (operands[0], QImode, size - 1);
    operands[1] = gen_int_mode (~0x80, QImode);
***************
*** 10658,10672 ****
    [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
  		   (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
  	      (clobber (reg:CC 17))])]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
- 
- (define_expand "abstf2"
-   [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
- 		   (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
- 	      (clobber (reg:CC 17))])]
    "TARGET_80387"
!   "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
  
  ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
  ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
--- 10093,10100 ----
    [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
  		   (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
  	      (clobber (reg:CC 17))])]
    "TARGET_80387"
!   "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
  
  ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
  ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
***************
*** 10675,10681 ****
    [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
  	(abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
     (clobber (reg:CC 17))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
     && ix86_unary_operator_ok (ABS, XFmode, operands)"
    "#")
  
--- 10103,10109 ----
    [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
  	(abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
     (clobber (reg:CC 17))]
!   "TARGET_80387
     && ix86_unary_operator_ok (ABS, XFmode, operands)"
    "#")
  
***************
*** 10699,10731 ****
     operands[0] = gen_rtx_REG (SImode,
  			      true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
  
- (define_insn "*abstf2_if"
-   [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
- 	(abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
-    (clobber (reg:CC 17))]
-   "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
-   "#")
- 
- (define_split
-   [(set (match_operand:TF 0 "fp_register_operand" "")
- 	(abs:TF (match_operand:TF 1 "register_operand" "")))
-    (clobber (reg:CC 17))]
-   "TARGET_80387 && reload_completed"
-   [(set (match_dup 0)
- 	(abs:TF (match_dup 1)))]
-   "")
- 
- (define_split
-   [(set (match_operand:TF 0 "register_and_not_any_fp_reg_operand" "")
- 	(abs:TF (match_operand:TF 1 "register_operand" "")))
-    (clobber (reg:CC 17))]
-   "TARGET_80387 && reload_completed"
-   [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
- 	      (clobber (reg:CC 17))])]
-   "operands[1] = GEN_INT (~0x8000);
-    operands[0] = gen_rtx_REG (SImode,
- 			      true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
- 
  (define_insn "*abssf2_1"
    [(set (match_operand:SF 0 "register_operand" "=f")
  	(abs:SF (match_operand:SF 1 "register_operand" "0")))]
--- 10127,10132 ----
***************
*** 10754,10760 ****
  (define_insn "*absxf2_1"
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(abs:XF (match_operand:XF 1 "register_operand" "0")))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && reload_completed"
    "fabs"
    [(set_attr "type" "fsgn")
     (set_attr "mode" "DF")])
--- 10155,10161 ----
  (define_insn "*absxf2_1"
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(abs:XF (match_operand:XF 1 "register_operand" "0")))]
!   "TARGET_80387 && reload_completed"
    "fabs"
    [(set_attr "type" "fsgn")
     (set_attr "mode" "DF")])
***************
*** 10763,10769 ****
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(abs:XF (float_extend:XF
  	  (match_operand:DF 1 "register_operand" "0"))))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
    "fabs"
    [(set_attr "type" "fsgn")
     (set_attr "mode" "XF")])
--- 10164,10170 ----
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(abs:XF (float_extend:XF
  	  (match_operand:DF 1 "register_operand" "0"))))]
!   "TARGET_80387"
    "fabs"
    [(set_attr "type" "fsgn")
     (set_attr "mode" "XF")])
***************
*** 10772,10803 ****
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(abs:XF (float_extend:XF
  	  (match_operand:SF 1 "register_operand" "0"))))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-   "fabs"
-   [(set_attr "type" "fsgn")
-    (set_attr "mode" "XF")])
- 
- (define_insn "*abstf2_1"
-   [(set (match_operand:TF 0 "register_operand" "=f")
- 	(abs:TF (match_operand:TF 1 "register_operand" "0")))]
-   "TARGET_80387 && reload_completed"
-   "fabs"
-   [(set_attr "type" "fsgn")
-    (set_attr "mode" "DF")])
- 
- (define_insn "*absextenddftf2"
-   [(set (match_operand:TF 0 "register_operand" "=f")
- 	(abs:TF (float_extend:TF
- 	  (match_operand:DF 1 "register_operand" "0"))))]
-   "TARGET_80387"
-   "fabs"
-   [(set_attr "type" "fsgn")
-    (set_attr "mode" "XF")])
- 
- (define_insn "*absextendsftf2"
-   [(set (match_operand:TF 0 "register_operand" "=f")
- 	(abs:TF (float_extend:TF
- 	  (match_operand:SF 1 "register_operand" "0"))))]
    "TARGET_80387"
    "fabs"
    [(set_attr "type" "fsgn")
--- 10173,10178 ----
***************
*** 14841,14847 ****
  	(match_operator:XF 3 "binary_fp_operator"
  			[(match_operand:XF 1 "register_operand" "%0")
  			 (match_operand:XF 2 "register_operand" "f")]))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
     && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
    "* return output_387_binary_op (insn, operands);"
    [(set (attr "type") 
--- 14216,14222 ----
  	(match_operator:XF 3 "binary_fp_operator"
  			[(match_operand:XF 1 "register_operand" "%0")
  			 (match_operand:XF 2 "register_operand" "f")]))]
!   "TARGET_80387
     && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
    "* return output_387_binary_op (insn, operands);"
    [(set (attr "type") 
***************
*** 14850,14868 ****
             (const_string "fop")))
     (set_attr "mode" "XF")])
  
- (define_insn "*fop_tf_comm"
-   [(set (match_operand:TF 0 "register_operand" "=f")
- 	(match_operator:TF 3 "binary_fp_operator"
- 			[(match_operand:TF 1 "register_operand" "%0")
- 			 (match_operand:TF 2 "register_operand" "f")]))]
-   "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
-   "* return output_387_binary_op (insn, operands);"
-   [(set (attr "type") 
-         (if_then_else (match_operand:TF 3 "mult_operator" "") 
-            (const_string "fmul")
-            (const_string "fop")))
-    (set_attr "mode" "XF")])
- 
  (define_insn "*fop_sf_1_nosse"
    [(set (match_operand:SF 0 "register_operand" "=f,f")
  	(match_operator:SF 3 "binary_fp_operator"
--- 14225,14230 ----
***************
*** 15117,15123 ****
  	(match_operator:XF 3 "binary_fp_operator"
  			[(match_operand:XF 1 "register_operand" "0,f")
  			 (match_operand:XF 2 "register_operand" "f,0")]))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
     && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
    "* return output_387_binary_op (insn, operands);"
    [(set (attr "type") 
--- 14479,14485 ----
  	(match_operator:XF 3 "binary_fp_operator"
  			[(match_operand:XF 1 "register_operand" "0,f")
  			 (match_operand:XF 2 "register_operand" "f,0")]))]
!   "TARGET_80387
     && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
    "* return output_387_binary_op (insn, operands);"
    [(set (attr "type") 
***************
*** 15129,15180 ****
                (const_string "fop")))
     (set_attr "mode" "XF")])
  
- (define_insn "*fop_tf_1"
-   [(set (match_operand:TF 0 "register_operand" "=f,f")
- 	(match_operator:TF 3 "binary_fp_operator"
- 			[(match_operand:TF 1 "register_operand" "0,f")
- 			 (match_operand:TF 2 "register_operand" "f,0")]))]
-   "TARGET_80387
-    && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
-   "* return output_387_binary_op (insn, operands);"
-   [(set (attr "type") 
-         (cond [(match_operand:TF 3 "mult_operator" "") 
-                  (const_string "fmul")
-                (match_operand:TF 3 "div_operator" "") 
-                  (const_string "fdiv")
-               ]
-               (const_string "fop")))
-    (set_attr "mode" "XF")])
- 
  (define_insn "*fop_xf_2"
    [(set (match_operand:XF 0 "register_operand" "=f,f")
  	(match_operator:XF 3 "binary_fp_operator"
  	   [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
! 	    (match_operand:XF 2 "register_operand" "0,0")]))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && TARGET_USE_FIOP"
!   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
!   [(set (attr "type") 
!         (cond [(match_operand:XF 3 "mult_operator" "") 
!                  (const_string "fmul")
!                (match_operand:XF 3 "div_operator" "") 
!                  (const_string "fdiv")
!               ]
!               (const_string "fop")))
!    (set_attr "fp_int_src" "true")
!    (set_attr "mode" "SI")
!    (set_attr "ppro_uops" "many")])
! 
! (define_insn "*fop_tf_2"
!   [(set (match_operand:TF 0 "register_operand" "=f,f")
! 	(match_operator:TF 3 "binary_fp_operator"
! 	   [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
! 	    (match_operand:TF 2 "register_operand" "0,0")]))]
    "TARGET_80387 && TARGET_USE_FIOP"
    "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
    [(set (attr "type") 
!         (cond [(match_operand:TF 3 "mult_operator" "") 
                   (const_string "fmul")
!                (match_operand:TF 3 "div_operator" "") 
                   (const_string "fdiv")
                ]
                (const_string "fop")))
--- 14491,14507 ----
                (const_string "fop")))
     (set_attr "mode" "XF")])
  
  (define_insn "*fop_xf_2"
    [(set (match_operand:XF 0 "register_operand" "=f,f")
  	(match_operator:XF 3 "binary_fp_operator"
  	   [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
! 	    (match_operand:XF 2 "register_operand" "0,0")]))]
    "TARGET_80387 && TARGET_USE_FIOP"
    "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
    [(set (attr "type") 
!         (cond [(match_operand:XF 3 "mult_operator" "") 
                   (const_string "fmul")
!                (match_operand:XF 3 "div_operator" "") 
                   (const_string "fdiv")
                ]
                (const_string "fop")))
***************
*** 15187,15193 ****
  	(match_operator:XF 3 "binary_fp_operator"
  	  [(match_operand:XF 1 "register_operand" "0,0")
  	   (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && TARGET_USE_FIOP"
    "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
    [(set (attr "type") 
          (cond [(match_operand:XF 3 "mult_operator" "") 
--- 14514,14520 ----
  	(match_operator:XF 3 "binary_fp_operator"
  	  [(match_operand:XF 1 "register_operand" "0,0")
  	   (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
!   "TARGET_80387 && TARGET_USE_FIOP"
    "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
    [(set (attr "type") 
          (cond [(match_operand:XF 3 "mult_operator" "") 
***************
*** 15200,15229 ****
     (set_attr "mode" "SI")
     (set_attr "ppro_uops" "many")])
  
- (define_insn "*fop_tf_3"
-   [(set (match_operand:TF 0 "register_operand" "=f,f")
- 	(match_operator:TF 3 "binary_fp_operator"
- 	  [(match_operand:TF 1 "register_operand" "0,0")
- 	   (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
-   "TARGET_80387 && TARGET_USE_FIOP"
-   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-   [(set (attr "type") 
-         (cond [(match_operand:TF 3 "mult_operator" "") 
-                  (const_string "fmul")
-                (match_operand:TF 3 "div_operator" "") 
-                  (const_string "fdiv")
-               ]
-               (const_string "fop")))
-    (set_attr "fp_int_src" "true")
-    (set_attr "mode" "SI")
-    (set_attr "ppro_uops" "many")])
- 
  (define_insn "*fop_xf_4"
    [(set (match_operand:XF 0 "register_operand" "=f,f")
  	(match_operator:XF 3 "binary_fp_operator"
  	   [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
  	    (match_operand:XF 2 "register_operand" "0,f")]))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
    "* return output_387_binary_op (insn, operands);"
    [(set (attr "type") 
          (cond [(match_operand:XF 3 "mult_operator" "") 
--- 14527,14538 ----
     (set_attr "mode" "SI")
     (set_attr "ppro_uops" "many")])
  
  (define_insn "*fop_xf_4"
    [(set (match_operand:XF 0 "register_operand" "=f,f")
  	(match_operator:XF 3 "binary_fp_operator"
  	   [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
  	    (match_operand:XF 2 "register_operand" "0,f")]))]
!   "TARGET_80387"
    "* return output_387_binary_op (insn, operands);"
    [(set (attr "type") 
          (cond [(match_operand:XF 3 "mult_operator" "") 
***************
*** 15234,15262 ****
                (const_string "fop")))
     (set_attr "mode" "SF")])
  
- (define_insn "*fop_tf_4"
-   [(set (match_operand:TF 0 "register_operand" "=f,f")
- 	(match_operator:TF 3 "binary_fp_operator"
- 	   [(float_extend:TF (match_operand 1 "nonimmediate_operand" "fm,0"))
- 	    (match_operand:TF 2 "register_operand" "0,f")]))]
-   "TARGET_80387"
-   "* return output_387_binary_op (insn, operands);"
-   [(set (attr "type") 
-         (cond [(match_operand:TF 3 "mult_operator" "") 
-                  (const_string "fmul")
-                (match_operand:TF 3 "div_operator" "") 
-                  (const_string "fdiv")
-               ]
-               (const_string "fop")))
-    (set_attr "mode" "SF")])
- 
  (define_insn "*fop_xf_5"
    [(set (match_operand:XF 0 "register_operand" "=f,f")
  	(match_operator:XF 3 "binary_fp_operator"
  	  [(match_operand:XF 1 "register_operand" "0,f")
  	   (float_extend:XF
  	    (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
    "* return output_387_binary_op (insn, operands);"
    [(set (attr "type") 
          (cond [(match_operand:XF 3 "mult_operator" "") 
--- 14543,14555 ----
                (const_string "fop")))
     (set_attr "mode" "SF")])
  
  (define_insn "*fop_xf_5"
    [(set (match_operand:XF 0 "register_operand" "=f,f")
  	(match_operator:XF 3 "binary_fp_operator"
  	  [(match_operand:XF 1 "register_operand" "0,f")
  	   (float_extend:XF
  	    (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
!   "TARGET_80387"
    "* return output_387_binary_op (insn, operands);"
    [(set (attr "type") 
          (cond [(match_operand:XF 3 "mult_operator" "") 
***************
*** 15267,15289 ****
                (const_string "fop")))
     (set_attr "mode" "SF")])
  
- (define_insn "*fop_tf_5"
-   [(set (match_operand:TF 0 "register_operand" "=f,f")
- 	(match_operator:TF 3 "binary_fp_operator"
- 	  [(match_operand:TF 1 "register_operand" "0,f")
- 	   (float_extend:TF
- 	    (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
-   "TARGET_80387"
-   "* return output_387_binary_op (insn, operands);"
-   [(set (attr "type") 
-         (cond [(match_operand:TF 3 "mult_operator" "") 
-                  (const_string "fmul")
-                (match_operand:TF 3 "div_operator" "") 
-                  (const_string "fdiv")
-               ]
-               (const_string "fop")))
-    (set_attr "mode" "SF")])
- 
  (define_insn "*fop_xf_6"
    [(set (match_operand:XF 0 "register_operand" "=f,f")
  	(match_operator:XF 3 "binary_fp_operator"
--- 14560,14565 ----
***************
*** 15291,15297 ****
  	    (match_operand 1 "register_operand" "0,f"))
  	   (float_extend:XF
  	    (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
    "* return output_387_binary_op (insn, operands);"
    [(set (attr "type") 
          (cond [(match_operand:XF 3 "mult_operator" "") 
--- 14567,14573 ----
  	    (match_operand 1 "register_operand" "0,f"))
  	   (float_extend:XF
  	    (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
!   "TARGET_80387"
    "* return output_387_binary_op (insn, operands);"
    [(set (attr "type") 
          (cond [(match_operand:XF 3 "mult_operator" "") 
***************
*** 15302,15325 ****
                (const_string "fop")))
     (set_attr "mode" "SF")])
  
- (define_insn "*fop_tf_6"
-   [(set (match_operand:TF 0 "register_operand" "=f,f")
- 	(match_operator:TF 3 "binary_fp_operator"
- 	  [(float_extend:TF
- 	    (match_operand 1 "register_operand" "0,f"))
- 	   (float_extend:TF
- 	    (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
-   "TARGET_80387"
-   "* return output_387_binary_op (insn, operands);"
-   [(set (attr "type") 
-         (cond [(match_operand:TF 3 "mult_operator" "") 
-                  (const_string "fmul")
-                (match_operand:TF 3 "div_operator" "") 
-                  (const_string "fdiv")
-               ]
-               (const_string "fop")))
-    (set_attr "mode" "SF")])
- 
  (define_split
    [(set (match_operand 0 "register_operand" "")
  	(match_operator 3 "binary_fp_operator"
--- 14578,14583 ----
***************
*** 15457,15473 ****
  (define_insn "sqrtxf2"
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387 
!    && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
!   "fsqrt"
!   [(set_attr "type" "fpspc")
!    (set_attr "mode" "XF")
!    (set_attr "athlon_decode" "direct")])
! 
! (define_insn "sqrttf2"
!   [(set (match_operand:TF 0 "register_operand" "=f")
! 	(sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
!   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
     && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
    "fsqrt"
    [(set_attr "type" "fpspc")
--- 14715,14721 ----
  (define_insn "sqrtxf2"
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
!   "TARGET_80387 && !TARGET_NO_FANCY_MATH_387 
     && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
    "fsqrt"
    [(set_attr "type" "fpspc")
***************
*** 15478,15494 ****
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(sqrt:XF (float_extend:XF
  		  (match_operand:DF 1 "register_operand" "0"))))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
!   "fsqrt"
!   [(set_attr "type" "fpspc")
!    (set_attr "mode" "XF")
!    (set_attr "athlon_decode" "direct")])
! 
! (define_insn "*sqrtextenddftf2"
!   [(set (match_operand:TF 0 "register_operand" "=f")
! 	(sqrt:TF (float_extend:TF
! 		  (match_operand:DF 1 "register_operand" "0"))))]
!   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
    "fsqrt"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")
--- 14726,14732 ----
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(sqrt:XF (float_extend:XF
  		  (match_operand:DF 1 "register_operand" "0"))))]
!   "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
    "fsqrt"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")
***************
*** 15498,15514 ****
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(sqrt:XF (float_extend:XF
  		  (match_operand:SF 1 "register_operand" "0"))))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
!   "fsqrt"
!   [(set_attr "type" "fpspc")
!    (set_attr "mode" "XF")
!    (set_attr "athlon_decode" "direct")])
! 
! (define_insn "*sqrtextendsftf2"
!   [(set (match_operand:TF 0 "register_operand" "=f")
! 	(sqrt:TF (float_extend:TF
! 		  (match_operand:SF 1 "register_operand" "0"))))]
!   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
    "fsqrt"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")
--- 14736,14742 ----
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(sqrt:XF (float_extend:XF
  		  (match_operand:SF 1 "register_operand" "0"))))]
!   "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
    "fsqrt"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")
***************
*** 15546,15561 ****
  (define_insn "sinxf2"
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
!   "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
!    && flag_unsafe_math_optimizations"
!   "fsin"
!   [(set_attr "type" "fpspc")
!    (set_attr "mode" "XF")])
! 
! (define_insn "sintf2"
!   [(set (match_operand:TF 0 "register_operand" "=f")
! 	(unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))]
!   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
     && flag_unsafe_math_optimizations"
    "fsin"
    [(set_attr "type" "fpspc")
--- 14774,14780 ----
  (define_insn "sinxf2"
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
!   "TARGET_80387 && !TARGET_NO_FANCY_MATH_387
     && flag_unsafe_math_optimizations"
    "fsin"
    [(set_attr "type" "fpspc")
***************
*** 15593,15608 ****
  (define_insn "cosxf2"
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
!   "!TARGET_128BIT_LONG_DOUBLE && ! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations"
!   "fcos"
!   [(set_attr "type" "fpspc")
!    (set_attr "mode" "XF")])
! 
! (define_insn "costf2"
!   [(set (match_operand:TF 0 "register_operand" "=f")
! 	(unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))]
!   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
     && flag_unsafe_math_optimizations"
    "fcos"
    [(set_attr "type" "fpspc")
--- 14812,14818 ----
  (define_insn "cosxf2"
    [(set (match_operand:XF 0 "register_operand" "=f")
  	(unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
!   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
     && flag_unsafe_math_optimizations"
    "fcos"
    [(set_attr "type" "fpspc")
***************
*** 15665,15671 ****
  	           UNSPEC_FPATAN))
     (clobber (match_scratch:XF 3 "=1"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations && ! TARGET_128BIT_LONG_DOUBLE"
    "fpatan"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")])
--- 14875,14881 ----
  	           UNSPEC_FPATAN))
     (clobber (match_scratch:XF 3 "=1"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations"
    "fpatan"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")])
***************
*** 15675,15681 ****
     (use (match_operand:XF 2 "register_operand" "0"))
     (use (match_operand:XF 1 "register_operand" "u"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations && ! TARGET_128BIT_LONG_DOUBLE"
  {
    rtx copy = gen_reg_rtx (XFmode);
    emit_move_insn (copy, operands[1]);
--- 14885,14891 ----
     (use (match_operand:XF 2 "register_operand" "0"))
     (use (match_operand:XF 1 "register_operand" "u"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations"
  {
    rtx copy = gen_reg_rtx (XFmode);
    emit_move_insn (copy, operands[1]);
***************
*** 15683,15722 ****
    DONE;
  })
  
- (define_insn "atan2tf3_1"
-   [(set (match_operand:TF 0 "register_operand" "=f")
-         (unspec:TF [(match_operand:TF 2 "register_operand" "0")
- 		    (match_operand:TF 1 "register_operand" "u")]
- 		   UNSPEC_FPATAN))
-    (clobber (match_scratch:TF 3 "=1"))]
-   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-    && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
-   "fpatan"
-   [(set_attr "type" "fpspc")
-    (set_attr "mode" "XF")])
- 
- (define_expand "atan2tf3"
-   [(use (match_operand:TF 0 "register_operand" "=f"))
-    (use (match_operand:TF 2 "register_operand" "0"))
-    (use (match_operand:TF 1 "register_operand" "u"))]
-   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-    && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
- {
-   rtx copy = gen_reg_rtx (TFmode);
-   emit_move_insn (copy, operands[1]);
-   emit_insn (gen_atan2tf3_1 (operands[0], copy, operands[2]));
-   DONE;
- })
- 
  (define_insn "*fyl2x_sfxf3"
    [(set (match_operand:SF 0 "register_operand" "=f")
           (unspec:SF [(match_operand:SF 2 "register_operand" "0")
! 		     (match_operand 1 "register_operand" "u")]
  		    UNSPEC_FYL2X))
     (clobber (match_scratch:SF 3 "=1"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations
!    && GET_MODE (operands[1]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)"
    "fyl2x"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "SF")])
--- 14893,14906 ----
    DONE;
  })
  
  (define_insn "*fyl2x_sfxf3"
    [(set (match_operand:SF 0 "register_operand" "=f")
           (unspec:SF [(match_operand:SF 2 "register_operand" "0")
! 		     (match_operand:XF 1 "register_operand" "u")]
  		    UNSPEC_FYL2X))
     (clobber (match_scratch:SF 3 "=1"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations"
    "fyl2x"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "SF")])
***************
*** 15724,15735 ****
  (define_insn "*fyl2x_dfxf3"
    [(set (match_operand:DF 0 "register_operand" "=f")
           (unspec:DF [(match_operand:DF 2 "register_operand" "0")
! 		     (match_operand 1 "register_operand" "u")]
  		    UNSPEC_FYL2X))
     (clobber (match_scratch:DF 3 "=1"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations
!    && GET_MODE (operands[1]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)"
    "fyl2x"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "DF")])
--- 14908,14918 ----
  (define_insn "*fyl2x_dfxf3"
    [(set (match_operand:DF 0 "register_operand" "=f")
           (unspec:DF [(match_operand:DF 2 "register_operand" "0")
! 		     (match_operand:XF 1 "register_operand" "u")]
  		    UNSPEC_FYL2X))
     (clobber (match_scratch:DF 3 "=1"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations"
    "fyl2x"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "DF")])
***************
*** 15741,15759 ****
  	           UNSPEC_FYL2X))
     (clobber (match_scratch:XF 3 "=1"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
!   "fyl2x"
!   [(set_attr "type" "fpspc")
!    (set_attr "mode" "XF")])
! 
! (define_insn "*fyl2x_tfxf3"
!   [(set (match_operand:TF 0 "register_operand" "=f")
! 	(unspec:TF [(match_operand:TF 2 "register_operand" "0")
! 		    (match_operand:TF 1 "register_operand" "u")]
! 		    UNSPEC_FYL2X))
!    (clobber (match_scratch:TF 3 "=1"))]
!   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
    "fyl2x"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")])
--- 14924,14930 ----
  	           UNSPEC_FYL2X))
     (clobber (match_scratch:XF 3 "=1"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations"
    "fyl2x"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")])
***************
*** 15768,15774 ****
  {
    rtx temp;
  
!   operands[2] = gen_reg_rtx (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode);
    temp = standard_80387_constant_rtx (4); /* fldln2 */
    emit_move_insn (operands[2], temp);
  })
--- 14939,14945 ----
  {
    rtx temp;
  
!   operands[2] = gen_reg_rtx (XFmode);
    temp = standard_80387_constant_rtx (4); /* fldln2 */
    emit_move_insn (operands[2], temp);
  })
***************
*** 15783,15789 ****
  {
    rtx temp;
  
!   operands[2] = gen_reg_rtx (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode);
    temp = standard_80387_constant_rtx (4); /* fldln2 */
    emit_move_insn (operands[2], temp);
  })
--- 14954,14960 ----
  {
    rtx temp;
  
!   operands[2] = gen_reg_rtx (XFmode);
    temp = standard_80387_constant_rtx (4); /* fldln2 */
    emit_move_insn (operands[2], temp);
  })
***************
*** 15794,15800 ****
  			       (match_dup 2)] UNSPEC_FYL2X))
  	      (clobber (match_scratch:XF 3 ""))])]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
  {
    rtx temp;
  
--- 14965,14971 ----
  			       (match_dup 2)] UNSPEC_FYL2X))
  	      (clobber (match_scratch:XF 3 ""))])]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations"
  {
    rtx temp;
  
***************
*** 15803,15847 ****
    emit_move_insn (operands[2], temp);
  })
  
- (define_expand "logtf2"
-   [(parallel [(set (match_operand:TF 0 "register_operand" "")
- 		   (unspec:TF [(match_operand:TF 1 "register_operand" "")
- 			       (match_dup 2)] UNSPEC_FYL2X))
- 	      (clobber (match_scratch:TF 3 ""))])]
-   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-    && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
- {
-   rtx temp;
- 
-   operands[2] = gen_reg_rtx (TFmode);
-   temp = standard_80387_constant_rtx (4); /* fldln2 */
-   emit_move_insn (operands[2], temp);
- })
- 
  (define_insn "*fscale_sfxf3"
    [(set (match_operand:SF 0 "register_operand" "=f")
! 	 (unspec:SF [(match_operand 2 "register_operand" "0")
! 		     (match_operand 1 "register_operand" "u")]
  		    UNSPEC_FSCALE))
     (clobber (match_scratch:SF 3 "=1"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations
!    && GET_MODE (operands[1]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)
!    && GET_MODE (operands[2]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)"
    "fscale\;fstp\t%y1"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "SF")])
  
  (define_insn "*fscale_dfxf3"
    [(set (match_operand:DF 0 "register_operand" "=f")
! 	 (unspec:DF [(match_operand 2 "register_operand" "0")
! 		     (match_operand 1 "register_operand" "u")]
  		    UNSPEC_FSCALE))
     (clobber (match_scratch:DF 3 "=1"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations
!    && GET_MODE (operands[1]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)
!    && GET_MODE (operands[2]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)"
    "fscale\;fstp\t%y1"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "DF")])
--- 14974,14999 ----
    emit_move_insn (operands[2], temp);
  })
  
  (define_insn "*fscale_sfxf3"
    [(set (match_operand:SF 0 "register_operand" "=f")
! 	 (unspec:SF [(match_operand:XF 2 "register_operand" "0")
! 		     (match_operand:XF 1 "register_operand" "u")]
  		    UNSPEC_FSCALE))
     (clobber (match_scratch:SF 3 "=1"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations"
    "fscale\;fstp\t%y1"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "SF")])
  
  (define_insn "*fscale_dfxf3"
    [(set (match_operand:DF 0 "register_operand" "=f")
! 	 (unspec:DF [(match_operand:XF 2 "register_operand" "0")
! 		     (match_operand:XF 1 "register_operand" "u")]
  		    UNSPEC_FSCALE))
     (clobber (match_scratch:DF 3 "=1"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations"
    "fscale\;fstp\t%y1"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "DF")])
***************
*** 15853,15871 ****
  	           UNSPEC_FSCALE))
     (clobber (match_scratch:XF 3 "=1"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
!   "fscale\;fstp\t%y1"
!   [(set_attr "type" "fpspc")
!    (set_attr "mode" "XF")])
! 
! (define_insn "*fscale_tf3"
!   [(set (match_operand:TF 0 "register_operand" "=f")
! 	(unspec:TF [(match_operand:TF 2 "register_operand" "0")
! 		    (match_operand:TF 1 "register_operand" "u")]
! 		   UNSPEC_FSCALE))
!    (clobber (match_scratch:TF 3 "=1"))]
!   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
    "fscale\;fstp\t%y1"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")])
--- 15005,15011 ----
  	           UNSPEC_FSCALE))
     (clobber (match_scratch:XF 3 "=1"))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations"
    "fscale\;fstp\t%y1"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")])
***************
*** 15875,15891 ****
  	(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
  	 UNSPEC_FRNDINT))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
!   "frndint"
!   [(set_attr "type" "fpspc")
!    (set_attr "mode" "XF")])
! 
! (define_insn "*frndinttf2"
!   [(set (match_operand:TF 0 "register_operand" "=f")
! 	(unspec:TF [(match_operand:TF 1 "register_operand" "0")]
! 	 UNSPEC_FRNDINT))]
!   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
    "frndint"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")])
--- 15015,15021 ----
  	(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
  	 UNSPEC_FRNDINT))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations"
    "frndint"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")])
***************
*** 15895,15911 ****
  	(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
  	 UNSPEC_F2XM1))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
!   "f2xm1"
!   [(set_attr "type" "fpspc")
!    (set_attr "mode" "XF")])
! 
! (define_insn "*f2xm1tf2"
!   [(set (match_operand:TF 0 "register_operand" "=f")
! 	(unspec:TF [(match_operand:TF 1 "register_operand" "0")]
! 	 UNSPEC_F2XM1))]
!   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
    "f2xm1"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")])
--- 15025,15031 ----
  	(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
  	 UNSPEC_F2XM1))]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations"
    "f2xm1"
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")])
***************
*** 15927,15938 ****
    rtx temp;
    int i;
  
-   if (TARGET_128BIT_LONG_DOUBLE)
-     {
-       emit_insn (gen_expsf2_tf (operands[0], operands[1]));
-       DONE;
-     }
- 
    for (i=2; i<10; i++)
      operands[i] = gen_reg_rtx (XFmode);
    temp = standard_80387_constant_rtx (5); /* fldl2e */
--- 15047,15052 ----
***************
*** 15940,15968 ****
    emit_move_insn (operands[8], CONST1_RTX (XFmode));  /* fld1 */
  })
  
- (define_expand "expsf2_tf"
-   [(set (match_dup 2)
- 	(float_extend:TF (match_operand:SF 1 "register_operand" "")))
-    (set (match_dup 4) (mult:TF (match_dup 2) (match_dup 3)))
-    (set (match_dup 5) (unspec:TF [(match_dup 4)] UNSPEC_FRNDINT))
-    (set (match_dup 6) (minus:TF (match_dup 4) (match_dup 5)))
-    (set (match_dup 7) (unspec:TF [(match_dup 6)] UNSPEC_F2XM1))
-    (set (match_dup 9) (plus:TF (match_dup 7) (match_dup 8)))
-    (parallel [(set (match_operand:SF 0 "register_operand" "")
- 		   (unspec:SF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
- 	      (clobber (match_scratch:SF 5 ""))])]
-   ""
- {
-   rtx temp;
-   int i;
- 
-   for (i=2; i<10; i++)
-     operands[i] = gen_reg_rtx (TFmode);
-   temp = standard_80387_constant_rtx (5); /* fldl2e */
-   emit_move_insn (operands[3], temp);
-   emit_move_insn (operands[8], CONST1_RTX (TFmode));  /* fld1 */
- })
- 
  (define_expand "expdf2"
    [(set (match_dup 2)
  	(float_extend:XF (match_operand:DF 1 "register_operand" "")))
--- 15054,15059 ----
***************
*** 15980,15991 ****
    rtx temp;
    int i;
  
-   if (TARGET_128BIT_LONG_DOUBLE)
-     {
-       emit_insn (gen_expdf2_tf (operands[0], operands[1]));
-       DONE;
-     }
- 
    for (i=2; i<10; i++)
      operands[i] = gen_reg_rtx (XFmode);
    temp = standard_80387_constant_rtx (5); /* fldl2e */
--- 15071,15076 ----
***************
*** 15993,16022 ****
    emit_move_insn (operands[8], CONST1_RTX (XFmode));  /* fld1 */
  })
  
- 
- (define_expand "expdf2_tf"
-   [(set (match_dup 2)
- 	(float_extend:TF (match_operand:DF 1 "register_operand" "")))
-    (set (match_dup 4) (mult:TF (match_dup 2) (match_dup 3)))
-    (set (match_dup 5) (unspec:TF [(match_dup 4)] UNSPEC_FRNDINT))
-    (set (match_dup 6) (minus:TF (match_dup 4) (match_dup 5)))
-    (set (match_dup 7) (unspec:TF [(match_dup 6)] UNSPEC_F2XM1))
-    (set (match_dup 9) (plus:TF (match_dup 7) (match_dup 8)))
-    (parallel [(set (match_operand:DF 0 "register_operand" "")
- 		   (unspec:DF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
- 	      (clobber (match_scratch:DF 5 ""))])]
-    ""
- {
-   rtx temp;
-   int i;
- 
-   for (i=2; i<10; i++)
-     operands[i] = gen_reg_rtx (TFmode);
-   temp = standard_80387_constant_rtx (5); /* fldl2e */
-   emit_move_insn (operands[3], temp);
-   emit_move_insn (operands[8], CONST1_RTX (TFmode));  /* fld1 */
- })
- 
  (define_expand "expxf2"
    [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
  			       (match_dup 2)))
--- 15078,15083 ----
***************
*** 16028,16034 ****
  		   (unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
  	      (clobber (match_scratch:XF 5 ""))])]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
  {
    rtx temp;
    int i;
--- 15089,15095 ----
  		   (unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
  	      (clobber (match_scratch:XF 5 ""))])]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations"
  {
    rtx temp;
    int i;
***************
*** 16053,16081 ****
    emit_move_insn (operands[2], CONST1_RTX (SFmode));  /* fld1 */
  })
  
- (define_expand "exptf2"
-   [(set (match_dup 3) (mult:TF (match_operand:TF 1 "register_operand" "")
- 			       (match_dup 2)))
-    (set (match_dup 4) (unspec:TF [(match_dup 3)] UNSPEC_FRNDINT))
-    (set (match_dup 5) (minus:TF (match_dup 3) (match_dup 4)))
-    (set (match_dup 6) (unspec:TF [(match_dup 5)] UNSPEC_F2XM1))
-    (set (match_dup 8) (plus:TF (match_dup 6) (match_dup 7)))
-    (parallel [(set (match_operand:TF 0 "register_operand" "")
- 		   (unspec:TF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
- 	      (clobber (match_scratch:TF 5 ""))])]
-   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-    && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
- {
-   rtx temp;
-   int i;
- 
-   for (i=2; i<9; i++)
-     operands[i] = gen_reg_rtx (TFmode);
-   temp = standard_80387_constant_rtx (5); /* fldl2e */
-   emit_move_insn (operands[2], temp);
-   emit_move_insn (operands[7], CONST1_RTX (TFmode));  /* fld1 */
- })
- 
  (define_expand "atandf2"
    [(parallel [(set (match_operand:DF 0 "register_operand" "")
  		   (unspec:DF [(match_dup 2)
--- 15114,15119 ----
***************
*** 16096,16119 ****
  		    UNSPEC_FPATAN))
  	      (clobber (match_scratch:XF 3 ""))])]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
  {
    operands[2] = gen_reg_rtx (XFmode);
    emit_move_insn (operands[2], CONST1_RTX (XFmode));  /* fld1 */
  })
- 
- (define_expand "atantf2"
-   [(parallel [(set (match_operand:TF 0 "register_operand" "")
- 		   (unspec:TF [(match_dup 2)
- 			       (match_operand:TF 1 "register_operand" "")]
- 		    UNSPEC_FPATAN))
- 	      (clobber (match_scratch:TF 3 ""))])]
-   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-    && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
- {
-   operands[2] = gen_reg_rtx (TFmode);
-   emit_move_insn (operands[2], CONST1_RTX (TFmode));  /* fld1 */
- })
  
  ;; Block operation instructions
  
--- 15134,15144 ----
  		    UNSPEC_FPATAN))
  	      (clobber (match_scratch:XF 3 ""))])]
    "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
!    && flag_unsafe_math_optimizations"
  {
    operands[2] = gen_reg_rtx (XFmode);
    emit_move_insn (operands[2], CONST1_RTX (XFmode));  /* fld1 */
  })
  
  ;; Block operation instructions
  
***************
*** 17364,17377 ****
  	(if_then_else:XF (match_operand 1 "comparison_operator" "")
  			 (match_operand:XF 2 "register_operand" "")
  			 (match_operand:XF 3 "register_operand" "")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_CMOVE"
-   "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
- 
- (define_expand "movtfcc"
-   [(set (match_operand:TF 0 "register_operand" "")
- 	(if_then_else:TF (match_operand 1 "comparison_operator" "")
- 			 (match_operand:TF 2 "register_operand" "")
- 			 (match_operand:TF 3 "register_operand" "")))]
    "TARGET_CMOVE"
    "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
  
--- 16389,16394 ----
***************
*** 17381,17399 ****
  				[(reg 17) (const_int 0)])
  		      (match_operand:XF 2 "register_operand" "f,0")
  		      (match_operand:XF 3 "register_operand" "0,f")))]
-   "!TARGET_128BIT_LONG_DOUBLE && TARGET_CMOVE"
-   "@
-    fcmov%F1\t{%2, %0|%0, %2}
-    fcmov%f1\t{%3, %0|%0, %3}"
-   [(set_attr "type" "fcmov")
-    (set_attr "mode" "XF")])
- 
- (define_insn "*movtfcc_1"
-   [(set (match_operand:TF 0 "register_operand" "=f,f")
- 	(if_then_else:TF (match_operator 1 "fcmov_comparison_operator" 
- 				[(reg 17) (const_int 0)])
- 		      (match_operand:TF 2 "register_operand" "f,0")
- 		      (match_operand:TF 3 "register_operand" "0,f")))]
    "TARGET_CMOVE"
    "@
     fcmov%F1\t{%2, %0|%0, %2}
--- 16398,16403 ----
***************
*** 19534,19539 ****
--- 18538,18555 ----
    DONE;
  })
  
+ (define_expand "movtf"
+   [(set (match_operand:TF 0 "nonimmediate_operand" "")
+ 	(match_operand:TF 1 "nonimmediate_operand" ""))]
+   "TARGET_64BIT"
+ {
+   if (TARGET_64BIT)
+     ix86_expand_move (TFmode, operands);
+   else
+     ix86_expand_vector_move (TFmode, operands);
+   DONE;
+ })
+ 
  (define_insn "movv2df_internal"
    [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
  	(match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
***************
*** 19919,19927 ****
--- 18935,18995 ----
  		   (const_string "TI"))]
  	       (const_string "DI")))])
  
+ (define_insn "*movtf_rex64"
+   [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm")
+ 	(match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
+   "TARGET_64BIT
+    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+ {
+   switch (which_alternative)
+     {
+     case 0:
+     case 1:
+       return "#";
+     case 2:
+       if (get_attr_mode (insn) == MODE_V4SF)
+ 	return "xorps\t%0, %0";
+       else
+ 	return "pxor\t%0, %0";
+     case 3:
+     case 4:
+       if (get_attr_mode (insn) == MODE_V4SF)
+ 	return "movaps\t{%1, %0|%0, %1}";
+       else
+ 	return "movdqa\t{%1, %0|%0, %1}";
+     default:
+       abort ();
+     }
+ }
+   [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
+    (set (attr "mode")
+         (cond [(eq_attr "alternative" "2,3")
+ 		 (if_then_else
+ 		   (ne (symbol_ref "optimize_size")
+ 		       (const_int 0))
+ 		   (const_string "V4SF")
+ 		   (const_string "TI"))
+ 	       (eq_attr "alternative" "4")
+ 		 (if_then_else
+ 		   (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
+ 			    (const_int 0))
+ 			(ne (symbol_ref "optimize_size")
+ 			    (const_int 0)))
+ 		   (const_string "V4SF")
+ 		   (const_string "TI"))]
+ 	       (const_string "DI")))])
+ 
  (define_split
    [(set (match_operand:TI 0 "nonimmediate_operand" "")
          (match_operand:TI 1 "general_operand" ""))]
+   "reload_completed && !SSE_REG_P (operands[0])
+    && !SSE_REG_P (operands[1])"
+   [(const_int 0)]
+   "ix86_split_long_move (operands); DONE;")
+ 
+ (define_split
+   [(set (match_operand:TF 0 "nonimmediate_operand" "")
+         (match_operand:TF 1 "general_operand" ""))]
    "reload_completed && !SSE_REG_P (operands[0])
     && !SSE_REG_P (operands[1])"
    [(const_int 0)]


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