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[committed] Fix unaligned load/store predicates
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: 30 Oct 2003 18:22:46 +0000
- Subject: [committed] Fix unaligned load/store predicates
Another one I noticed while experimenting. Bootstrapped & regression
tested on mips64{,el}-linux-gnu, installed as obvious.
Richard
* config/mips/mips.md (mov_lwl): Use memory_operand where appropriate.
(mov_lwr, mov_swl, mov_swr): Likewise.
(mov_ldl, mov_ldr, mov_sdl, mov_sdr): Likewise.
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.204
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.204 mips.md
--- config/mips/mips.md 19 Oct 2003 07:52:10 -0000 1.204
+++ config/mips/mips.md 30 Oct 2003 18:08:06 -0000
@@ -4061,8 +4061,8 @@ (define_expand "insv"
(define_insn "mov_lwl"
[(set (match_operand:SI 0 "register_operand" "=d")
- (unspec:SI [(match_operand:BLK 1 "general_operand" "m")
- (match_operand:QI 2 "general_operand" "m")]
+ (unspec:SI [(match_operand:BLK 1 "memory_operand" "m")
+ (match_operand:QI 2 "memory_operand" "m")]
UNSPEC_LWL))]
"!TARGET_MIPS16"
"lwl\t%0,%2"
@@ -4072,8 +4072,8 @@ (define_insn "mov_lwl"
(define_insn "mov_lwr"
[(set (match_operand:SI 0 "register_operand" "=d")
- (unspec:SI [(match_operand:BLK 1 "general_operand" "m")
- (match_operand:QI 2 "general_operand" "m")
+ (unspec:SI [(match_operand:BLK 1 "memory_operand" "m")
+ (match_operand:QI 2 "memory_operand" "m")
(match_operand:SI 3 "register_operand" "0")]
UNSPEC_LWR))]
"!TARGET_MIPS16"
@@ -4085,7 +4085,7 @@ (define_insn "mov_lwr"
(define_insn "mov_swl"
[(set (match_operand:BLK 0 "memory_operand" "=m")
(unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ")
- (match_operand:QI 2 "general_operand" "m")]
+ (match_operand:QI 2 "memory_operand" "m")]
UNSPEC_SWL))]
"!TARGET_MIPS16"
"swl\t%z1,%2"
@@ -4095,7 +4095,7 @@ (define_insn "mov_swl"
(define_insn "mov_swr"
[(set (match_operand:BLK 0 "memory_operand" "+m")
(unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ")
- (match_operand:QI 2 "general_operand" "m")
+ (match_operand:QI 2 "memory_operand" "m")
(match_dup 0)]
UNSPEC_SWR))]
"!TARGET_MIPS16"
@@ -4106,8 +4106,8 @@ (define_insn "mov_swr"
(define_insn "mov_ldl"
[(set (match_operand:DI 0 "register_operand" "=d")
- (unspec:DI [(match_operand:BLK 1 "general_operand" "m")
- (match_operand:QI 2 "general_operand" "m")]
+ (unspec:DI [(match_operand:BLK 1 "memory_operand" "m")
+ (match_operand:QI 2 "memory_operand" "m")]
UNSPEC_LDL))]
"TARGET_64BIT && !TARGET_MIPS16"
"ldl\t%0,%2"
@@ -4116,8 +4116,8 @@ (define_insn "mov_ldl"
(define_insn "mov_ldr"
[(set (match_operand:DI 0 "register_operand" "=d")
- (unspec:DI [(match_operand:BLK 1 "general_operand" "m")
- (match_operand:QI 2 "general_operand" "m")
+ (unspec:DI [(match_operand:BLK 1 "memory_operand" "m")
+ (match_operand:QI 2 "memory_operand" "m")
(match_operand:DI 3 "register_operand" "0")]
UNSPEC_LDR))]
"TARGET_64BIT && !TARGET_MIPS16"
@@ -4129,7 +4129,7 @@ (define_insn "mov_ldr"
(define_insn "mov_sdl"
[(set (match_operand:BLK 0 "memory_operand" "=m")
(unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ")
- (match_operand:QI 2 "general_operand" "m")]
+ (match_operand:QI 2 "memory_operand" "m")]
UNSPEC_SDL))]
"TARGET_64BIT && !TARGET_MIPS16"
"sdl\t%z1,%2"
@@ -4139,7 +4139,7 @@ (define_insn "mov_sdl"
(define_insn "mov_sdr"
[(set (match_operand:BLK 0 "memory_operand" "+m")
(unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ")
- (match_operand:QI 2 "general_operand" "m")
+ (match_operand:QI 2 "memory_operand" "m")
(match_dup 0)]
UNSPEC_SDR))]
"TARGET_64BIT && !TARGET_MIPS16"