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S/390: Allow reg+offset as shift count
- From: "Ulrich Weigand" <weigand at i1 dot informatik dot uni-erlangen dot de>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sun, 19 Oct 2003 00:26:35 +0200 (CEST)
- Subject: S/390: Allow reg+offset as shift count
Hello,
the shift-type instructions on s390 accept an address as shift count;
this means it is possible to use 'base register + offset' as count
in one single instruction. This patch enables gcc to make full use
of this feature, employing a new EXTRA_ADDRESS_CONSTRAINT.
Bootstrapped/regtested on s390-ibm-linux and s390x-ibm-linux.
Bye,
Ulrich
ChangeLog:
* config/s390/s390-protos.h (shift_count_operand): Add prototype.
* config/s390/s390.c (shift_count_operand): New function.
(s390_extra_constraint): Use it to implement 'Y' constraint.
(print_shift_count_operand): New function.
(print_operand): Use it to implement '%Y'.
* config/s390/s390.h (EXTRA_ADDRESS_CONSTRAINT): Add 'Y' constraint.
(PREDICATE_CODES): Add shift_count_operand.
* config/s390/s390.md ("rotldi3"): Merge alternatives,
using "shift_count_operand" predicate and "Y" constraint,
and "%Y" to output the combined shift count.
("rotlsi3"): Likewise.
("ashldi3", "*ashldi3_31", "*ashldi3_64"): Likewise.
("ashrdi3", "*ashrdi3_31", "*ashrdi3_64", "*ashrdi3_cc_31",
"*ashrdi3_cc_64", "*ashrdi3_cconly_31", "*ashrdi3_cconly_64"): Likewise.
("ashlsi3", "ashrsi3", "*ashrsi3_cc", "*ashrsi3_cconly"): Likewise.
("lshrdi3", "*lshrdi3_31", "*lshrdi3_64"): Likewise.
("lshrsi3"): Likewise.
Index: gcc/config/s390/s390-protos.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390-protos.h,v
retrieving revision 1.37
diff -c -p -r1.37 s390-protos.h
*** gcc/config/s390/s390-protos.h 14 Oct 2003 22:55:36 -0000 1.37
--- gcc/config/s390/s390-protos.h 18 Oct 2003 19:59:41 -0000
*************** extern int consttable_operand (rtx, enum
*** 36,41 ****
--- 36,42 ----
extern int larl_operand (rtx, enum machine_mode);
extern int s_operand (rtx, enum machine_mode);
extern int s_imm_operand (rtx, enum machine_mode);
+ extern int shift_count_operand (rtx, enum machine_mode);
extern int bras_sym_operand (rtx, enum machine_mode);
extern int load_multiple_operation (rtx, enum machine_mode);
extern int store_multiple_operation (rtx, enum machine_mode);
Index: gcc/config/s390/s390.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.c,v
retrieving revision 1.115
diff -c -p -r1.115 s390.c
*** gcc/config/s390/s390.c 14 Oct 2003 22:55:36 -0000 1.115
--- gcc/config/s390/s390.c 18 Oct 2003 19:59:42 -0000
*************** static int s390_short_displacement (rtx)
*** 211,216 ****
--- 211,217 ----
static int s390_decompose_address (rtx, struct s390_address *);
static rtx get_thread_pointer (void);
static rtx legitimize_tls_address (rtx, rtx);
+ static void print_shift_count_operand (FILE *, rtx);
static const char *get_some_local_dynamic_name (void);
static int get_some_local_dynamic_name_1 (rtx *, void *);
static int reg_used_in_mem_p (int, rtx);
*************** s_imm_operand (register rtx op, enum mac
*** 1274,1279 ****
--- 1275,1319 ----
return general_s_operand (op, mode, 1);
}
+ /* Return true if OP a valid shift count operand.
+ OP is the current operation.
+ MODE is the current operation mode. */
+
+ int
+ shift_count_operand (rtx op, enum machine_mode mode)
+ {
+ HOST_WIDE_INT offset = 0;
+
+ if (! check_mode (op, &mode))
+ return 0;
+
+ /* We can have an integer constant, an address register,
+ or a sum of the two. Note that reload already checks
+ that any register present is an address register, so
+ we just check for any register here. */
+ if (GET_CODE (op) == CONST_INT)
+ {
+ offset = INTVAL (op);
+ op = NULL_RTX;
+ }
+ if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
+ {
+ offset = INTVAL (XEXP (op, 1));
+ op = XEXP (op, 0);
+ }
+ while (op && GET_CODE (op) == SUBREG)
+ op = SUBREG_REG (op);
+ if (op && GET_CODE (op) != REG)
+ return 0;
+
+ /* Unfortunately we have to reject constants that are invalid
+ for an address, or else reload will get confused. */
+ if (!DISP_IN_RANGE (offset))
+ return 0;
+
+ return 1;
+ }
+
/* Return true if DISP is a valid short displacement. */
static int
*************** s390_extra_constraint (rtx op, int c)
*** 1383,1388 ****
--- 1423,1431 ----
return 0;
break;
+ case 'Y':
+ return shift_count_operand (op, VOIDmode);
+
default:
return 0;
}
*************** s390_delegitimize_address (rtx orig_x)
*** 3281,3286 ****
--- 3324,3363 ----
return orig_x;
}
+ /* Output shift count operand OP to stdio stream FILE. */
+
+ static void
+ print_shift_count_operand (FILE *file, rtx op)
+ {
+ HOST_WIDE_INT offset = 0;
+
+ /* We can have an integer constant, an address register,
+ or a sum of the two. */
+ if (GET_CODE (op) == CONST_INT)
+ {
+ offset = INTVAL (op);
+ op = NULL_RTX;
+ }
+ if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
+ {
+ offset = INTVAL (XEXP (op, 1));
+ op = XEXP (op, 0);
+ }
+ while (op && GET_CODE (op) == SUBREG)
+ op = SUBREG_REG (op);
+
+ /* Sanity check. */
+ if (op && (GET_CODE (op) != REG
+ || REGNO (op) >= FIRST_PSEUDO_REGISTER
+ || REGNO_REG_CLASS (REGNO (op)) != ADDR_REGS))
+ abort ();
+
+ /* Shift counts are truncated to the low six bits anyway. */
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & 63);
+ if (op)
+ fprintf (file, "(%s)", reg_names[REGNO (op)]);
+ }
+
/* Locate some local-dynamic symbol still in use by this function
so that we can print its name in local-dynamic base patterns. */
*************** print_operand_address (FILE *file, rtx a
*** 3451,3456 ****
--- 3528,3534 ----
'R': print only the base register of a memory reference.
'N': print the second word of a DImode operand.
'M': print the second word of a TImode operand.
+ 'Y': print shift count operand.
'b': print integer X as if it's an unsigned byte.
'x': print integer X as if it's an unsigned word.
*************** print_operand (FILE *file, rtx x, int co
*** 3540,3545 ****
--- 3618,3627 ----
else
abort ();
break;
+
+ case 'Y':
+ print_shift_count_operand (file, x);
+ return;
}
switch (GET_CODE (x))
Index: gcc/config/s390/s390.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.h,v
retrieving revision 1.87
diff -c -p -r1.87 s390.h
*** gcc/config/s390/s390.h 14 Oct 2003 22:55:36 -0000 1.87
--- gcc/config/s390/s390.h 18 Oct 2003 19:59:43 -0000
*************** extern const enum reg_class regclass_map
*** 544,550 ****
#define EXTRA_MEMORY_CONSTRAINT(C, STR) \
((C) == 'Q' || (C) == 'R' || (C) == 'S' || (C) == 'T')
#define EXTRA_ADDRESS_CONSTRAINT(C, STR) \
! ((C) == 'U' || (C) == 'W')
/* Stack layout and calling conventions. */
--- 544,550 ----
#define EXTRA_MEMORY_CONSTRAINT(C, STR) \
((C) == 'Q' || (C) == 'R' || (C) == 'S' || (C) == 'T')
#define EXTRA_ADDRESS_CONSTRAINT(C, STR) \
! ((C) == 'U' || (C) == 'W' || (C) == 'Y')
/* Stack layout and calling conventions. */
*************** do { \
*** 1023,1028 ****
--- 1023,1029 ----
#define PREDICATE_CODES \
{"s_operand", { SUBREG, MEM }}, \
{"s_imm_operand", { CONST_INT, CONST_DOUBLE, SUBREG, MEM }}, \
+ {"shift_count_operand", { REG, SUBREG, PLUS, CONST_INT }}, \
{"bras_sym_operand",{ SYMBOL_REF, CONST }}, \
{"larl_operand", { SYMBOL_REF, CONST, CONST_INT, CONST_DOUBLE }}, \
{"load_multiple_operation", {PARALLEL}}, \
Index: gcc/config/s390/s390.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.md,v
retrieving revision 1.80
diff -c -p -r1.80 s390.md
*** gcc/config/s390/s390.md 14 Oct 2003 22:55:36 -0000 1.80
--- gcc/config/s390/s390.md 18 Oct 2003 19:59:45 -0000
***************
*** 5982,5994 ****
;
(define_insn "rotldi3"
! [(set (match_operand:DI 0 "register_operand" "=d,d")
! (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
! (match_operand:SI 2 "nonmemory_operand" "J,a")))]
"TARGET_64BIT"
! "@
! rllg\t%0,%1,%c2
! rllg\t%0,%1,0(%2)"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
--- 5982,5992 ----
;
(define_insn "rotldi3"
! [(set (match_operand:DI 0 "register_operand" "=d")
! (rotate:DI (match_operand:DI 1 "register_operand" "d")
! (match_operand:SI 2 "shift_count_operand" "Y")))]
"TARGET_64BIT"
! "rllg\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
***************
*** 5997,6009 ****
;
(define_insn "rotlsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
! (match_operand:SI 2 "nonmemory_operand" "J,a")))]
"TARGET_CPU_ZARCH"
! "@
! rll\t%0,%1,%c2
! rll\t%0,%1,0(%2)"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
--- 5995,6005 ----
;
(define_insn "rotlsi3"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (rotate:SI (match_operand:SI 1 "register_operand" "d")
! (match_operand:SI 2 "shift_count_operand" "Y")))]
"TARGET_CPU_ZARCH"
! "rll\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
***************
*** 6019,6047 ****
(define_expand "ashldi3"
[(set (match_operand:DI 0 "register_operand" "")
(ashift:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:SI 2 "nonmemory_operand" "")))]
""
"")
(define_insn "*ashldi3_31"
! [(set (match_operand:DI 0 "register_operand" "=d,d")
! (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
! (match_operand:SI 2 "nonmemory_operand" "J,a")))]
"!TARGET_64BIT"
! "@
! sldl\t%0,%c2
! sldl\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "*ashldi3_64"
! [(set (match_operand:DI 0 "register_operand" "=d,d")
! (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
! (match_operand:SI 2 "nonmemory_operand" "J,a")))]
"TARGET_64BIT"
! "@
! sllg\t%0,%1,%2
! sllg\t%0,%1,0(%2)"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
--- 6015,6039 ----
(define_expand "ashldi3"
[(set (match_operand:DI 0 "register_operand" "")
(ashift:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:SI 2 "shift_count_operand" "")))]
""
"")
(define_insn "*ashldi3_31"
! [(set (match_operand:DI 0 "register_operand" "=d")
! (ashift:DI (match_operand:DI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_operand" "Y")))]
"!TARGET_64BIT"
! "sldl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "*ashldi3_64"
! [(set (match_operand:DI 0 "register_operand" "=d")
! (ashift:DI (match_operand:DI 1 "register_operand" "d")
! (match_operand:SI 2 "shift_count_operand" "Y")))]
"TARGET_64BIT"
! "sllg\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
***************
*** 6053,6138 ****
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:SI 2 "nonmemory_operand" "")))
(clobber (reg:CC 33))])]
""
"")
(define_insn "*ashrdi3_cc_31"
[(set (reg 33)
! (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
! (match_operand:SI 2 "nonmemory_operand" "J,a"))
(const_int 0)))
! (set (match_operand:DI 0 "register_operand" "=d,d")
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
! "@
! srda\t%0,%c2
! srda\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_cconly_31"
[(set (reg 33)
! (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
! (match_operand:SI 2 "nonmemory_operand" "J,a"))
(const_int 0)))
! (clobber (match_scratch:DI 0 "=d,d"))]
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
! "@
! srda\t%0,%c2
! srda\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_31"
! [(set (match_operand:DI 0 "register_operand" "=d,d")
! (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
! (match_operand:SI 2 "nonmemory_operand" "J,a")))
(clobber (reg:CC 33))]
"!TARGET_64BIT"
! "@
! srda\t%0,%c2
! srda\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_cc_64"
[(set (reg 33)
! (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
! (match_operand:SI 2 "nonmemory_operand" "J,a"))
(const_int 0)))
! (set (match_operand:DI 0 "register_operand" "=d,d")
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
! "@
! srag\t%0,%1,%c2
! srag\t%0,%1,0(%2)"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_cconly_64"
[(set (reg 33)
! (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
! (match_operand:SI 2 "nonmemory_operand" "J,a"))
(const_int 0)))
! (clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
! "@
! srag\t%0,%1,%c2
! srag\t%0,%1,0(%2)"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_64"
! [(set (match_operand:DI 0 "register_operand" "=d,d")
! (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
! (match_operand:SI 2 "nonmemory_operand" "J,a")))
(clobber (reg:CC 33))]
"TARGET_64BIT"
! "@
! srag\t%0,%1,%c2
! srag\t%0,%1,0(%2)"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
--- 6045,6118 ----
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:SI 2 "shift_count_operand" "")))
(clobber (reg:CC 33))])]
""
"")
(define_insn "*ashrdi3_cc_31"
[(set (reg 33)
! (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
! (set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
! "srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_cconly_31"
[(set (reg 33)
! (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
! (clobber (match_scratch:DI 0 "=d"))]
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
! "srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_31"
! [(set (match_operand:DI 0 "register_operand" "=d")
! (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_operand" "Y")))
(clobber (reg:CC 33))]
"!TARGET_64BIT"
! "srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_cc_64"
[(set (reg 33)
! (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
! (match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
! (set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
! "srag\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_cconly_64"
[(set (reg 33)
! (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
! (match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
! (clobber (match_scratch:DI 0 "=d"))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
! "srag\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
(define_insn "*ashrdi3_64"
! [(set (match_operand:DI 0 "register_operand" "=d")
! (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
! (match_operand:SI 2 "shift_count_operand" "Y")))
(clobber (reg:CC 33))]
"TARGET_64BIT"
! "srag\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
***************
*** 6142,6154 ****
;
(define_insn "ashlsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
! (match_operand:SI 2 "nonmemory_operand" "J,a")))]
""
! "@
! sll\t%0,%c2
! sll\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
--- 6122,6132 ----
;
(define_insn "ashlsi3"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (ashift:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_operand" "Y")))]
""
! "sll\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
***************
*** 6158,6198 ****
(define_insn "*ashrsi3_cc"
[(set (reg 33)
! (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
! (match_operand:SI 2 "nonmemory_operand" "J,a"))
(const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d")
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCSmode)"
! "@
! sra\t%0,%c2
! sra\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "*ashrsi3_cconly"
[(set (reg 33)
! (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
! (match_operand:SI 2 "nonmemory_operand" "J,a"))
(const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
! "@
! sra\t%0,%c2
! sra\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "ashrsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
! (match_operand:SI 2 "nonmemory_operand" "J,a")))
(clobber (reg:CC 33))]
""
! "@
! sra\t%0,%c2
! sra\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
--- 6136,6170 ----
(define_insn "*ashrsi3_cc"
[(set (reg 33)
! (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d")
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCSmode)"
! "sra\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "*ashrsi3_cconly"
[(set (reg 33)
! (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_operand" "Y"))
(const_int 0)))
! (clobber (match_scratch:SI 0 "=d"))]
"s390_match_ccmode(insn, CCSmode)"
! "sra\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "ashrsi3"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_operand" "Y")))
(clobber (reg:CC 33))]
""
! "sra\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
***************
*** 6208,6237 ****
(define_expand "lshrdi3"
[(set (match_operand:DI 0 "register_operand" "")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:SI 2 "nonmemory_operand" "")))]
""
"")
(define_insn "*lshrdi3_31"
! [(set (match_operand:DI 0 "register_operand" "=d,d")
! (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
! (match_operand:SI 2 "nonmemory_operand" "J,a")))]
"!TARGET_64BIT"
! "@
! srdl\t%0,%c2
! srdl\t%0,0(%2)"
! [(set_attr "op_type" "RS,RS")
(set_attr "atype" "reg")])
(define_insn "*lshrdi3_64"
! [(set (match_operand:DI 0 "register_operand" "=d,d")
! (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
! (match_operand:SI 2 "nonmemory_operand" "J,a")))]
"TARGET_64BIT"
! "@
! srlg\t%0,%1,%c2
! srlg\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE,RSE")
(set_attr "atype" "reg")])
;
--- 6180,6205 ----
(define_expand "lshrdi3"
[(set (match_operand:DI 0 "register_operand" "")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:SI 2 "shift_count_operand" "")))]
""
"")
(define_insn "*lshrdi3_31"
! [(set (match_operand:DI 0 "register_operand" "=d")
! (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_operand" "Y")))]
"!TARGET_64BIT"
! "srdl\t%0,%Y2"
! [(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "*lshrdi3_64"
! [(set (match_operand:DI 0 "register_operand" "=d")
! (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
! (match_operand:SI 2 "shift_count_operand" "Y")))]
"TARGET_64BIT"
! "srlg\t%0,%1,%Y2"
! [(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
;
***************
*** 6239,6251 ****
;
(define_insn "lshrsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
! (match_operand:SI 2 "nonmemory_operand" "J,a")))]
""
! "@
! srl\t%0,%c2
! srl\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
--- 6207,6217 ----
;
(define_insn "lshrsi3"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "shift_count_operand" "Y")))]
""
! "srl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
--
Dr. Ulrich Weigand
weigand@informatik.uni-erlangen.de