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[PATCH] ARM. Add serveral <op>_cbranch patterns


Now that conditional-execution support doesn't abort when the condition is 
too complex, this patch adds several patterns for Thumb so that sequences 
such as

	sub	r0, r0, #4
	cmp	r0, #0
	bne	<dest>

can be optimized to

	sub	r0, r0, #4
	bne	<dest>

since Thumb data-processing instructions generally set the condition codes.

Overall, this patch is worth about a 1% saving in code space.  I'd expect 
a corresponding (or perhaps better) improvement in Thumb performance.

A problem revealed during testing is that the Thumb epilogue rtl does not 
describe the registers being restored by the exit sequence.  This causes 
the flow2 life information to be inaccurately computed and can thus cause 
problems when register-renaming is done.  I've added a patch to the Thumb 
epilogue expander so that it emits a clobber for each register that is 
restored by the final epilogue insn, and a use of the link register if 
that is not saved on the stack.  While it would be better to emit the 
epilogue insns in full, this does at least mean that flow2 information is 
now correctly computed.

R.

2003-10-17  Richard Earnshaw  <rearnsha@arm.com>

	* arm-modes.def (CC_Nmode): New condition code mode.
	* arm.c (thumb_condition_code): Delete.
	(arm_select_cc_mode): Handle single-bit test for Thumb.
	(arm_print_operand, cases 'd' and 'D'): Don't special case the 
	condition code logic for Thumb.
	(get_arm_condition_code): Handle CC_Nmode.
	(thumb_cbrch_target_operand): New function.
	* arm.h (PREDICATE_CODES): Add thumb_cbrch_target_operand.
	* arm-protos.h (thumb_cbrch_target_operand): Add prototype.
	* arm.md: Add Thumb split patterns for zero_extract and
	sign_extract.
	(tbit_cbranch, andsi3_cbranch_scratch, andsi3_cbranch)
	(orrsi3_cbranch_scratch, orrsi3_cbranch, xorsi3_cbranch_scratch)
	(xorsi3_cbranch, addsi3_cbranch, addsi3_cbranch_scratch)
	(subsi3_cbranch, subsi3_cbranch_scratch): New Thumb patterns.
	(cbranchne_decr1): Re-work to use CC_Nmode.

	* arm.c (thumb_expand_epilogue): Add clobbers of registers restored 
	by the return instruction.  Add a use of the link register if it
	wasn't stored.


Attachment: op_cbranch.patch
Description: op_cbranch.patch


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