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ia64 XFmode patch rides again (need ia64-linux testing)
- From: "Zack Weinberg" <zack at codesourcery dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Jim Wilson <wilson at specifixinc dot com>, Richard Henderson <rth at redhat dot com>
- Date: Thu, 16 Oct 2003 15:10:21 -0700
- Subject: ia64 XFmode patch rides again (need ia64-linux testing)
Having now, I hope, removed all the obstructions, this patch once
again attempts to support simultaneous use of 80-bit and 128-bit
floating point in the ia64 back end. It's much the same as it was the
last time -- replace TFmode with XFmode in all hardware insns
referring to the extended floating point type; use TFmode exclusively
for software emulated IEEE quad. However, instead of using
ROUND_TYPE_ALIGN as before, I am using ADJUST_BYTESIZE and
ADJUST_ALIGNMENT declarations in ia64-modes.def, which *should* mean
that everything obeys the requirements.
As before, all libgcc __*tf* functions have forwarding stubs to the
corresponding __*xf* function. I do not, however, attempt to define
the names of the TFmode emulator functions in this patch, except on
HP-UX. I think it is plausible to use the HP-UX names universally,
but we can discuss that separately.
Also, I removed the logic to inline calls to _U_Qfcmp; this can come
separately and only complicates the patch.
I believe that the ADJUST_BYTESIZE and ADJUST_ALIGNMENT settings are
100% compatible with the defined ia64 ABIs, but a careful second eye
would be appreciated. Note, in particular, that XFmode only gets
4-byte alignment if TARGET_ILP32 && !TARGET_HPUX, which may require
machine description changes if any such target ever comes into
existence (there is none now).
Bootstrapped without regression (C and C++; --disable-libstdcxx-pch)
for ia64-hpux11.23. I need testing on ia64-linux.
zw
* c-common.c (registered_builtin_types): New static.
(c_register_builtin_type): Add type to registered_builtin_types.
(c_common_type_for_mode): Check registered_builtin_types for
more possibilities.
* optabs.c (init_floating_libfuncs): Consider all MODE_FLOAT
modes, not just the ones corresponding to C float, double,
long double.
* config/ia64/ia64-modes.def: Define XFmode as well as TFmode.
Use ADJUST_BYTESIZE and ADJUST_ALIGNMENT to set size and
alignment of XF and TF modes in compliance with ia64 ABIs.
Can now hardwire the format of both modes.
* config/ia64/ia64.c: Change TFmode to XFmode wherever appropriate.
(general_tfmode_operand, destination_tfmode_operand)
(tfreg_or_fp01_operand, spill_tfmode_operand): Rename to
general_xfmode_operand, destination_xfmode_operand,
xfreg_or_fp01_operand, spill_xfmode_operand respectively.
(ia64_init_builtins): Make TYPE_PRECISION of fpreg_type
and float80_type be 96 so they get XFmode. Use !TARGET_HPUX,
not INTEL_EXTENDED_IEEE_FORMAT, to decide how to define
__float128.
* config/ia64/ia64.h: Default TARGET_HPUX to 0.
Change TFmode to XFmode wherever appropriate. Remove all
references to INTEL_EXTENDED_IEEE_FORMAT.
(LONG_DOUBLE_TYPE_SIZE): Varies with TARGET_HPUX.
(LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Define (always 96).
(PREDICATE_CODES): Update to match function renames.
* config/ia64/ia64.md: Change TF to XF throughout; rename all
patterns to match. Remove all references to
INTEL_EXTENDED_IEEE_FORMAT. Update predicate calls to match
function renames.
* config/ia64/ia64-protos.c: Update all prototypes to match
renamed functions.
* config/ia64/hpux.h: Redefine TARGET_HPUX to 1.
Remove all references to INTEL_EXTENDED_IEEE_FORMAT.
* config/ia64/lib1funcs.asm: Add __divxf3 as new name for
__divtf3; keep old name for backward compatibility.
(L__compat): New section providing forwarding stubs for
__fixtfti, __fixunstfti, __floattitf.
* config/ia64/t-ia64: Add __compat to LIB1ASMFUNCS.
===================================================================
Index: c-common.c
--- c-common.c 12 Oct 2003 22:09:20 -0000 1.463
+++ c-common.c 16 Oct 2003 22:09:36 -0000
@@ -1828,6 +1828,10 @@ c_common_type_for_size (unsigned int bit
return 0;
}
+/* Used for communication between c_common_type_for_mode and
+ c_register_builtin_type. */
+static GTY(()) tree registered_builtin_types;
+
/* Return a data type that has machine mode MODE.
If the mode is an integer,
then UNSIGNEDP selects between signed and unsigned types. */
@@ -1835,6 +1839,8 @@ c_common_type_for_size (unsigned int bit
tree
c_common_type_for_mode (enum machine_mode mode, int unsignedp)
{
+ tree t;
+
if (mode == TYPE_MODE (integer_type_node))
return unsignedp ? unsigned_type_node : integer_type_node;
@@ -1923,6 +1929,10 @@ c_common_type_for_mode (enum machine_mod
break;
}
+ for (t = registered_builtin_types; t; t = TREE_CHAIN (t))
+ if (TYPE_MODE (TREE_VALUE (t)) == mode)
+ return TREE_VALUE (t);
+
return 0;
}
@@ -2051,6 +2061,8 @@ c_register_builtin_type (tree type, cons
if (!TYPE_NAME (type))
TYPE_NAME (type) = decl;
pushdecl (decl);
+
+ registered_builtin_types = tree_cons (0, type, registered_builtin_types);
}
===================================================================
Index: optabs.c
--- optabs.c 11 Oct 2003 19:00:49 -0000 1.200
+++ optabs.c 16 Oct 2003 22:09:37 -0000
@@ -5019,18 +5019,7 @@ init_integral_libfuncs (optab optable, c
static void
init_floating_libfuncs (optab optable, const char *opname, int suffix)
{
- enum machine_mode fmode, dmode, lmode;
-
- fmode = float_type_node ? TYPE_MODE (float_type_node) : VOIDmode;
- dmode = double_type_node ? TYPE_MODE (double_type_node) : VOIDmode;
- lmode = long_double_type_node ? TYPE_MODE (long_double_type_node) : VOIDmode;
-
- if (fmode != VOIDmode)
- init_libfuncs (optable, fmode, fmode, opname, suffix);
- if (dmode != fmode && dmode != VOIDmode)
- init_libfuncs (optable, dmode, dmode, opname, suffix);
- if (lmode != dmode && lmode != VOIDmode)
- init_libfuncs (optable, lmode, lmode, opname, suffix);
+ init_libfuncs (optable, MIN_MODE_FLOAT, MAX_MODE_FLOAT, opname, suffix);
}
/* Initialize the libfunc fields of an entire group of entries of an
===================================================================
Index: config/ia64/hpux.h
--- config/ia64/hpux.h 2 Oct 2003 00:44:22 -0000 1.33
+++ config/ia64/hpux.h 16 Oct 2003 22:09:37 -0000
@@ -25,6 +25,10 @@ Boston, MA 02111-1307, USA. */
#define TARGET_VERSION fprintf (stderr, " (IA-64) HP-UX");
+/* Enable HPUX ABI quirks. */
+#undef TARGET_HPUX
+#define TARGET_HPUX 1
+
/* Target OS builtins. */
#define TARGET_OS_CPP_BUILTINS() \
do { \
@@ -106,7 +110,8 @@ do { \
returned just like a char variable and that is wrong on HP-UX
IA64. */
-#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) (TREE_CODE (TREE_TYPE (FIELD)) != REAL_TYPE || (MODE == TFmode && !INTEL_EXTENDED_IEEE_FORMAT))
+#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
+ (TREE_CODE (TREE_TYPE (FIELD)) != REAL_TYPE || MODE == TFmode)
/* ASM_OUTPUT_EXTERNAL_LIBCALL defaults to just a globalize_label call,
but that doesn't put out the @function type information which causes
@@ -186,10 +191,6 @@ do { \
/* ia64 HPUX has the float and long double forms of math functions. */
#undef TARGET_C99_FUNCTIONS
#define TARGET_C99_FUNCTIONS 1
-
-/* We are using IEEE quad precision, not a double-extended with padding. */
-#undef INTEL_EXTENDED_IEEE_FORMAT
-#define INTEL_EXTENDED_IEEE_FORMAT 0
#define TARGET_INIT_LIBFUNCS ia64_hpux_init_libfuncs
===================================================================
Index: config/ia64/ia64-modes.def
--- config/ia64/ia64-modes.def 13 Oct 2003 21:16:27 -0000 1.3
+++ config/ia64/ia64-modes.def 16 Oct 2003 22:09:37 -0000
@@ -1,5 +1,5 @@
/* Definitions of target machine GNU compiler. IA-64 version.
- Copyright (C) 2002 Free Software Foundation, Inc.
+ Copyright (C) 2002, 2003 Free Software Foundation, Inc.
Contributed by James E. Wilson <wilson@cygnus.com> and
David Mosberger <davidm@hpl.hp.com>.
@@ -20,8 +20,41 @@ along with GCC; see the file COPYING. I
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
-/* hpux will override this in ia64_override_options. */
-FLOAT_MODE (TF, 16, ieee_extended_intel_128_format);
+/* IA64 requires both XF and TF modes.
+ XFmode is __float80 is IEEE extended; TFmode is __float128
+ is IEEE quad.
+
+ IEEE extended is 128 bits wide, except in ILP32 mode, but we
+ have to say it's 12 bytes so that the bitsize and wider_mode
+ tables are correctly set up. We correct its size below. */
+
+FLOAT_MODE (XF, 12, ieee_extended_intel_128_format);
+FLOAT_MODE (TF, 16, ieee_quad_format);
+
+/* The above produces:
+
+ mode ILP32 size/align LP64 size/align
+ XF 12/4 12/4
+ TF 16/16 16/16
+
+ psABI expectations:
+
+ mode ILP32 size/align LP64 size/align
+ XF - 16/16
+ TF - -
+
+ HPUX expectations:
+
+ mode ILP32 size/align LP64 size/align
+ XF 16/16 16/16
+ TF 16/8 -
+
+ We fix this up here. */
+
+ADJUST_BYTESIZE (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 12 : 16);
+ADJUST_ALIGNMENT (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 4 : 16);
+
+ADJUST_ALIGNMENT (TF, (TARGET_ILP32 && TARGET_HPUX) ? 8 : 16);
/* 256-bit integer mode is needed for STACK_SAVEAREA_MODE. */
INT_MODE (OI, 32);
===================================================================
Index: config/ia64/ia64-protos.h
--- config/ia64/ia64-protos.h 17 Aug 2003 10:00:04 -0000 1.61
+++ config/ia64/ia64-protos.h 16 Oct 2003 22:09:37 -0000
@@ -70,9 +70,9 @@ extern int predicate_operator (rtx, enum
extern int ar_lc_reg_operand (rtx, enum machine_mode);
extern int ar_ccv_reg_operand (rtx, enum machine_mode);
extern int ar_pfs_reg_operand (rtx, enum machine_mode);
-extern int general_tfmode_operand (rtx, enum machine_mode);
-extern int destination_tfmode_operand (rtx, enum machine_mode);
-extern int tfreg_or_fp01_operand (rtx, enum machine_mode);
+extern int general_xfmode_operand (rtx, enum machine_mode);
+extern int destination_xfmode_operand (rtx, enum machine_mode);
+extern int xfreg_or_fp01_operand (rtx, enum machine_mode);
extern int basereg_operand (rtx, enum machine_mode);
extern rtx ia64_expand_move (rtx, rtx);
@@ -81,7 +81,7 @@ extern int addp4_optimize_ok (rtx, rtx);
extern void ia64_emit_cond_move (rtx, rtx, rtx);
extern int ia64_depz_field_mask (rtx, rtx);
extern rtx ia64_split_timode (rtx[], rtx, rtx);
-extern rtx spill_tfmode_operand (rtx, int);
+extern rtx spill_xfmode_operand (rtx, int);
extern rtx ia64_expand_compare (enum rtx_code, enum machine_mode);
extern void ia64_expand_call (rtx, rtx, rtx, int);
extern void ia64_split_call (rtx, rtx, rtx, rtx, rtx, int, int);
===================================================================
Index: config/ia64/ia64.c
--- config/ia64/ia64.c 14 Oct 2003 19:25:49 -0000 1.254
+++ config/ia64/ia64.c 16 Oct 2003 22:09:37 -0000
@@ -923,7 +923,7 @@ ar_pfs_reg_operand (register rtx op, enu
/* Like general_operand, but don't allow (mem (addressof)). */
int
-general_tfmode_operand (rtx op, enum machine_mode mode)
+general_xfmode_operand (rtx op, enum machine_mode mode)
{
if (! general_operand (op, mode))
return 0;
@@ -935,7 +935,7 @@ general_tfmode_operand (rtx op, enum mac
/* Similarly. */
int
-destination_tfmode_operand (rtx op, enum machine_mode mode)
+destination_xfmode_operand (rtx op, enum machine_mode mode)
{
if (! destination_operand (op, mode))
return 0;
@@ -947,7 +947,7 @@ destination_tfmode_operand (rtx op, enum
/* Similarly. */
int
-tfreg_or_fp01_operand (rtx op, enum machine_mode mode)
+xfreg_or_fp01_operand (rtx op, enum machine_mode mode)
{
if (GET_CODE (op) == SUBREG)
return 0;
@@ -1430,34 +1430,34 @@ ia64_split_timode (rtx out[2], rtx in, r
}
}
-/* ??? Fixing GR->FR TFmode moves during reload is hard. You need to go
+/* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
through memory plus an extra GR scratch register. Except that you can
either get the first from SECONDARY_MEMORY_NEEDED or the second from
SECONDARY_RELOAD_CLASS, but not both.
We got into problems in the first place by allowing a construct like
- (subreg:TF (reg:TI)), which we got from a union containing a long double.
+ (subreg:XF (reg:TI)), which we got from a union containing a long double.
This solution attempts to prevent this situation from occurring. When
we see something like the above, we spill the inner register to memory. */
rtx
-spill_tfmode_operand (rtx in, int force)
+spill_xfmode_operand (rtx in, int force)
{
if (GET_CODE (in) == SUBREG
&& GET_MODE (SUBREG_REG (in)) == TImode
&& GET_CODE (SUBREG_REG (in)) == REG)
{
rtx mem = gen_mem_addressof (SUBREG_REG (in), NULL_TREE, /*rescan=*/true);
- return gen_rtx_MEM (TFmode, copy_to_reg (XEXP (mem, 0)));
+ return gen_rtx_MEM (XFmode, copy_to_reg (XEXP (mem, 0)));
}
else if (force && GET_CODE (in) == REG)
{
rtx mem = gen_mem_addressof (in, NULL_TREE, /*rescan=*/true);
- return gen_rtx_MEM (TFmode, copy_to_reg (XEXP (mem, 0)));
+ return gen_rtx_MEM (XFmode, copy_to_reg (XEXP (mem, 0)));
}
else if (GET_CODE (in) == MEM
&& GET_CODE (XEXP (in, 0)) == ADDRESSOF)
- return change_address (in, TFmode, copy_to_reg (XEXP (in, 0)));
+ return change_address (in, XFmode, copy_to_reg (XEXP (in, 0)));
else
return in;
}
@@ -2679,7 +2679,7 @@ ia64_expand_prologue (void)
{
if (cfa_off & 15)
abort ();
- reg = gen_rtx_REG (TFmode, regno);
+ reg = gen_rtx_REG (XFmode, regno);
do_spill (gen_fr_spill_x, reg, cfa_off, reg);
cfa_off -= 16;
}
@@ -2849,7 +2849,7 @@ ia64_expand_epilogue (int sibcall_p)
{
if (cfa_off & 15)
abort ();
- reg = gen_rtx_REG (TFmode, regno);
+ reg = gen_rtx_REG (XFmode, regno);
do_restore (gen_fr_restore_x, reg, cfa_off);
cfa_off -= 16;
}
@@ -3305,7 +3305,7 @@ hfa_element_mode (tree type, int nested)
types though. */
case COMPLEX_TYPE:
if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
- && (TYPE_MODE (type) != TCmode || INTEL_EXTENDED_IEEE_FORMAT))
+ && TYPE_MODE (type) != TCmode)
return mode_for_size (GET_MODE_UNIT_SIZE (TYPE_MODE (type))
* BITS_PER_UNIT, MODE_FLOAT, 0);
else
@@ -3314,7 +3314,7 @@ hfa_element_mode (tree type, int nested)
case REAL_TYPE:
/* We want to return VOIDmode for raw REAL_TYPEs, but the actual
mode if this is contained within an aggregate. */
- if (nested && (TYPE_MODE (type) != TFmode || INTEL_EXTENDED_IEEE_FORMAT))
+ if (nested && TYPE_MODE (type) != TFmode)
return TYPE_MODE (type);
else
return VOIDmode;
@@ -3482,8 +3482,8 @@ ia64_function_arg (CUMULATIVE_ARGS *cum,
/* Integral and aggregates go in general registers. If we have run out of
FR registers, then FP values must also go in general registers. This can
happen when we have a SFmode HFA. */
- else if (((mode == TFmode) && ! INTEL_EXTENDED_IEEE_FORMAT)
- || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
+ else if (mode == TFmode
+ || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
{
int byte_size = ((mode == BLKmode)
? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
@@ -3784,8 +3784,7 @@ ia64_function_value (tree valtype, tree
else
return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
}
- else if (FLOAT_TYPE_P (valtype) &&
- ((mode != TFmode) || INTEL_EXTENDED_IEEE_FORMAT))
+ else if (FLOAT_TYPE_P (valtype) && mode != TFmode)
return gen_rtx_REG (mode, FR_ARG_FIRST);
else
{
@@ -4188,11 +4187,11 @@ ia64_register_move_cost (enum machine_mo
to = from, from = tmp;
}
- /* Moving from FR<->GR in TFmode must be more expensive than 2,
+ /* Moving from FR<->GR in XFmode must be more expensive than 2,
so that we get secondary memory reloads. Between FR_REGS,
we have to make this at least as expensive as MEMORY_MOVE_COST
to avoid spectacularly poor register class preferencing. */
- if (mode == TFmode)
+ if (mode == XFmode)
{
if (to != GR_REGS || from != GR_REGS)
return MEMORY_MOVE_COST (mode, to, 0);
@@ -4521,10 +4520,6 @@ ia64_override_options (void)
ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
init_machine_status = ia64_init_machine_status;
-
- /* Tell the compiler which flavor of TFmode we're using. */
- if (!INTEL_EXTENDED_IEEE_FORMAT)
- REAL_MODE_FORMAT (TFmode) = &ieee_quad_format;
}
static enum attr_itanium_class ia64_safe_itanium_class (rtx);
@@ -7717,26 +7712,20 @@ ia64_init_builtins (void)
/* The __fpreg type. */
fpreg_type = make_node (REAL_TYPE);
- /* ??? Once the IA64 back end supports both 80-bit and 128-bit
- floating types, this type should have XFmode, not TFmode.
- TYPE_PRECISION should be 80 bits, not 128. And, the back end
- should know to load/save __fpreg variables using the ldf.fill and
- stf.spill instructions. */
- TYPE_PRECISION (fpreg_type) = 128;
+ /* ??? The back end should know to load/save __fpreg variables using
+ the ldf.fill and stf.spill instructions. */
+ TYPE_PRECISION (fpreg_type) = 96;
layout_type (fpreg_type);
(*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
/* The __float80 type. */
float80_type = make_node (REAL_TYPE);
- /* ??? Once the IA64 back end supports both 80-bit and 128-bit
- floating types, this type should have XFmode, not TFmode.
- TYPE_PRECISION should be 80 bits, not 128. */
- TYPE_PRECISION (float80_type) = 128;
+ TYPE_PRECISION (float80_type) = 96;
layout_type (float80_type);
(*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
/* The __float128 type. */
- if (INTEL_EXTENDED_IEEE_FORMAT)
+ if (!TARGET_HPUX)
{
tree float128_type = make_node (REAL_TYPE);
TYPE_PRECISION (float128_type) = 128;
@@ -7744,7 +7733,7 @@ ia64_init_builtins (void)
(*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
}
else
- /* This is a synonym for "long double". */
+ /* Under HPUX, this is a synonym for "long double". */
(*lang_hooks.types.register_builtin_type) (long_double_type_node,
"__float128");
@@ -8345,8 +8334,10 @@ ia64_hpux_init_libfuncs (void)
set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
+ set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad");
set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
+ set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80");
set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl");
set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
===================================================================
Index: config/ia64/ia64.h
--- config/ia64/ia64.h 10 Oct 2003 22:44:41 -0000 1.158
+++ config/ia64/ia64.h 16 Oct 2003 22:09:37 -0000
@@ -135,6 +135,7 @@ extern int ia64_tls_size;
#define TARGET_TLS64 (ia64_tls_size == 64)
#define TARGET_EARLY_STOP_BITS (target_flags & MASK_EARLY_STOP_BITS)
+#define TARGET_HPUX 0
#define TARGET_HPUX_LD 0
#ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS
@@ -417,11 +418,11 @@ while (0)
#define DOUBLE_TYPE_SIZE 64
-#define LONG_DOUBLE_TYPE_SIZE 128
+/* long double is XFmode normally, TFmode for HPUX. */
+#define LONG_DOUBLE_TYPE_SIZE (TARGET_HPUX ? 128 : 96)
-/* By default we use the 80-bit Intel extended float format packaged
- in a 128-bit entity. */
-#define INTEL_EXTENDED_IEEE_FORMAT 1
+/* We always want the XFmode operations from libgcc2.c. */
+#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
#define DEFAULT_SIGNED_CHAR 1
@@ -779,7 +780,7 @@ while (0)
((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
: PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
: PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
- : FR_REGNO_P (REGNO) && (MODE) == TFmode && INTEL_EXTENDED_IEEE_FORMAT ? 1 \
+ : FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* A C expression that is nonzero if it is permissible to store a value of mode
@@ -791,10 +792,10 @@ while (0)
GET_MODE_CLASS (MODE) != MODE_CC && \
(MODE) != TImode && \
(MODE) != BImode && \
- ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT) \
+ (MODE) != TFmode \
: PR_REGNO_P (REGNO) ? \
(MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
- : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \
+ : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != XFmode \
: AR_REGNO_P (REGNO) ? (MODE) == DImode \
: BR_REGNO_P (REGNO) ? (MODE) == DImode \
: 0)
@@ -807,11 +808,11 @@ while (0)
ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
zero. */
/* Don't tie integer and FP modes, as that causes us to get integer registers
- allocated for FP instructions. TFmode only supported in FP registers so
+ allocated for FP instructions. XFmode only supported in FP registers so
we can't tie it with any other modes. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
(GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
- && (((MODE1) == TFmode) == ((MODE2) == TFmode)) \
+ && (((MODE1) == XFmode) == ((MODE2) == XFmode)) \
&& (((MODE1) == BImode) == ((MODE2) == BImode)))
/* Handling Leaf Functions */
@@ -1011,12 +1012,12 @@ enum reg_class
into a register of CLASS2. */
#if 0
-/* ??? May need this, but since we've disallowed TFmode in GR_REGS,
+/* ??? May need this, but since we've disallowed XFmode in GR_REGS,
I'm not quite sure how it could be invoked. The normal problems
with unions should be solved with the addressof fiddling done by
- movtf and friends. */
+ movxf and friends. */
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
- ((MODE) == TFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
+ ((MODE) == XFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
|| ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
#endif
@@ -1026,7 +1027,7 @@ enum reg_class
#define CLASS_MAX_NREGS(CLASS, MODE) \
((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
- : ((CLASS) == FR_REGS && (MODE) == TFmode) ? 1 \
+ : ((CLASS) == FR_REGS && (MODE) == XFmode) ? 1 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* In FP regs, we can't change FP values to integer values and vice
@@ -1389,7 +1390,7 @@ do { \
gen_rtx_REG (MODE, \
(((GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \
- ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT)) \
+ (MODE) != TFmode) \
? FR_RET_FIRST : GR_RET_FIRST))
/* A C expression that is nonzero if REGNO is the number of a hard register in
@@ -2214,9 +2215,9 @@ do { \
{ "ar_lc_reg_operand", {REG}}, \
{ "ar_ccv_reg_operand", {REG}}, \
{ "ar_pfs_reg_operand", {REG}}, \
-{ "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
-{ "destination_tfmode_operand", {SUBREG, REG, MEM}}, \
-{ "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \
+{ "general_xfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
+{ "destination_xfmode_operand", {SUBREG, REG, MEM}}, \
+{ "xfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \
{ "basereg_operand", {SUBREG, REG}},
/* An alias for a machine mode name. This is the machine mode that elements of
===================================================================
Index: config/ia64/ia64.md
--- config/ia64/ia64.md 14 Oct 2003 19:25:54 -0000 1.113
+++ config/ia64/ia64.md 16 Oct 2003 22:09:38 -0000
@@ -756,19 +756,19 @@
;; With no offsettable memory references, we've got to have a scratch
;; around to play with the second word if the variable winds up in GRs.
-(define_expand "movtf"
- [(set (match_operand:TF 0 "general_operand" "")
- (match_operand:TF 1 "general_operand" ""))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_expand "movxf"
+ [(set (match_operand:XF 0 "general_operand" "")
+ (match_operand:XF 1 "general_operand" ""))]
+ ""
{
- /* We must support TFmode loads into general registers for stdarg/vararg
+ /* We must support XFmode loads into general registers for stdarg/vararg
and unprototyped calls. We split them into DImode loads for convenience.
- We don't need TFmode stores from general regs, because a stdarg/vararg
+ We don't need XFmode stores from general regs, because a stdarg/vararg
routine does a block store to memory of unnamed arguments. */
if (GET_CODE (operands[0]) == REG
&& GR_REGNO_P (REGNO (operands[0])))
{
- /* We're hoping to transform everything that deals with TFmode
+ /* We're hoping to transform everything that deals with XFmode
quantities and GR registers early in the compiler. */
if (no_new_pseudos)
abort ();
@@ -787,15 +787,15 @@
if (GET_CODE (operands[1]) == CONST_DOUBLE)
{
emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0])),
- operand_subword (operands[1], 0, 0, TFmode));
+ operand_subword (operands[1], 0, 0, XFmode));
emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0]) + 1),
- operand_subword (operands[1], 1, 0, TFmode));
+ operand_subword (operands[1], 1, 0, XFmode));
DONE;
}
/* If the quantity is in a register not known to be GR, spill it. */
- if (register_operand (operands[1], TFmode))
- operands[1] = spill_tfmode_operand (operands[1], 1);
+ if (register_operand (operands[1], XFmode))
+ operands[1] = spill_xfmode_operand (operands[1], 1);
if (GET_CODE (operands[1]) == MEM)
{
@@ -814,20 +814,20 @@
if (! reload_in_progress && ! reload_completed)
{
- operands[0] = spill_tfmode_operand (operands[0], 0);
- operands[1] = spill_tfmode_operand (operands[1], 0);
+ operands[0] = spill_xfmode_operand (operands[0], 0);
+ operands[1] = spill_xfmode_operand (operands[1], 0);
if (! ia64_move_ok (operands[0], operands[1]))
- operands[1] = force_reg (TFmode, operands[1]);
+ operands[1] = force_reg (XFmode, operands[1]);
}
})
;; ??? There's no easy way to mind volatile acquire/release semantics.
-(define_insn "*movtf_internal"
- [(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
- (match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
- "INTEL_EXTENDED_IEEE_FORMAT && ia64_move_ok (operands[0], operands[1])"
+(define_insn "*movxf_internal"
+ [(set (match_operand:XF 0 "destination_xfmode_operand" "=f,f, m")
+ (match_operand:XF 1 "general_xfmode_operand" "fG,m,fG"))]
+ "ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
ldfe %0 = %1%P1
@@ -919,17 +919,17 @@
"fnorm.d %0 = %1"
[(set_attr "itanium_class" "fmac")])
-(define_insn "extendsftf2"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (float_extend:TF (match_operand:SF 1 "fr_register_operand" "f")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "extendsfxf2"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (float_extend:XF (match_operand:SF 1 "fr_register_operand" "f")))]
+ ""
"fnorm %0 = %1"
[(set_attr "itanium_class" "fmac")])
-(define_insn "extenddftf2"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (float_extend:TF (match_operand:DF 1 "fr_register_operand" "f")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "extenddfxf2"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (float_extend:XF (match_operand:DF 1 "fr_register_operand" "f")))]
+ ""
"fnorm %0 = %1"
[(set_attr "itanium_class" "fmac")])
@@ -940,45 +940,29 @@
"fnorm.s %0 = %1"
[(set_attr "itanium_class" "fmac")])
-(define_insn "trunctfsf2"
+(define_insn "truncxfsf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
- (float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (float_truncate:SF (match_operand:XF 1 "fr_register_operand" "f")))]
+ ""
"fnorm.s %0 = %1"
[(set_attr "itanium_class" "fmac")])
-(define_insn "trunctfdf2"
+(define_insn "truncxfdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
- (float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (float_truncate:DF (match_operand:XF 1 "fr_register_operand" "f")))]
+ ""
"fnorm.d %0 = %1"
[(set_attr "itanium_class" "fmac")])
;; Convert between signed integer types and floating point.
-(define_insn "floatditf2"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "floatdixf2"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (float:XF (match_operand:DI 1 "fr_register_operand" "f")))]
+ ""
"fcvt.xf %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
-;; ??? Suboptimal. This should be split somehow.
-(define_insn "floatdidf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (float:DF (match_operand:DI 1 "register_operand" "f")))]
- "!INTEL_EXTENDED_IEEE_FORMAT"
- "fcvt.xf %0 = %1\;;;\;%,fnorm.d %0 = %0"
- [(set_attr "itanium_class" "fcvtfx")])
-
-;; ??? Suboptimal. This should be split somehow.
-(define_insn "floatdisf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (float:SF (match_operand:DI 1 "register_operand" "f")))]
- "!INTEL_EXTENDED_IEEE_FORMAT"
- "fcvt.xf %0 = %1\;;;\;%,fnorm.s %0 = %0"
- [(set_attr "itanium_class" "fcvtfx")])
-
(define_insn "fix_truncsfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
@@ -993,18 +977,18 @@
"fcvt.fx.trunc %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
-(define_insn "fix_trunctfdi2"
+(define_insn "fix_truncxfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
- (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))]
+ ""
"fcvt.fx.trunc %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
-(define_insn "fix_trunctfdi2_alts"
+(define_insn "fix_truncxfdi2_alts"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
- (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
+ (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))
(use (match_operand:SI 2 "const_int_operand" ""))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ ""
"fcvt.fx.trunc.s%2 %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
@@ -1024,10 +1008,10 @@
"fcvt.xuf.d %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
-(define_insn "floatunsditf2"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "floatunsdixf2"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "f")))]
+ ""
"fcvt.xuf %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
@@ -1045,18 +1029,18 @@
"fcvt.fxu.trunc %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
-(define_insn "fixuns_trunctfdi2"
+(define_insn "fixuns_truncxfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
- (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))]
+ ""
"fcvt.fxu.trunc %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
-(define_insn "fixuns_trunctfdi2_alts"
+(define_insn "fixuns_truncxfdi2_alts"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
- (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
+ (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))
(use (match_operand:SI 2 "const_int_operand" ""))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ ""
"fcvt.fxu.trunc.s%2 %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
@@ -1921,32 +1905,32 @@
[(set (match_operand:SI 0 "register_operand" "")
(div:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
+ "TARGET_INLINE_INT_DIV"
{
- rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
+ rtx op1_xf, op2_xf, op0_xf, op0_di, twon34;
REAL_VALUE_TYPE twon34_r;
- op0_tf = gen_reg_rtx (TFmode);
+ op0_xf = gen_reg_rtx (XFmode);
op0_di = gen_reg_rtx (DImode);
if (CONSTANT_P (operands[1]))
operands[1] = force_reg (SImode, operands[1]);
- op1_tf = gen_reg_rtx (TFmode);
- expand_float (op1_tf, operands[1], 0);
+ op1_xf = gen_reg_rtx (XFmode);
+ expand_float (op1_xf, operands[1], 0);
if (CONSTANT_P (operands[2]))
operands[2] = force_reg (SImode, operands[2]);
- op2_tf = gen_reg_rtx (TFmode);
- expand_float (op2_tf, operands[2], 0);
+ op2_xf = gen_reg_rtx (XFmode);
+ expand_float (op2_xf, operands[2], 0);
/* 2^-34 */
real_2expN (&twon34_r, -34);
- twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, TFmode);
- twon34 = force_reg (TFmode, twon34);
+ twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, XFmode);
+ twon34 = force_reg (XFmode, twon34);
- emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34));
+ emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
- emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
+ emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx));
emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
DONE;
})
@@ -1955,7 +1939,7 @@
[(set (match_operand:SI 0 "register_operand" "")
(mod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
+ "TARGET_INLINE_INT_DIV"
{
rtx op2_neg, op1_di, div;
@@ -1978,32 +1962,32 @@
[(set (match_operand:SI 0 "register_operand" "")
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
+ "TARGET_INLINE_INT_DIV"
{
- rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
+ rtx op1_xf, op2_xf, op0_xf, op0_di, twon34;
REAL_VALUE_TYPE twon34_r;
- op0_tf = gen_reg_rtx (TFmode);
+ op0_xf = gen_reg_rtx (XFmode);
op0_di = gen_reg_rtx (DImode);
if (CONSTANT_P (operands[1]))
operands[1] = force_reg (SImode, operands[1]);
- op1_tf = gen_reg_rtx (TFmode);
- expand_float (op1_tf, operands[1], 1);
+ op1_xf = gen_reg_rtx (XFmode);
+ expand_float (op1_xf, operands[1], 1);
if (CONSTANT_P (operands[2]))
operands[2] = force_reg (SImode, operands[2]);
- op2_tf = gen_reg_rtx (TFmode);
- expand_float (op2_tf, operands[2], 1);
+ op2_xf = gen_reg_rtx (XFmode);
+ expand_float (op2_xf, operands[2], 1);
/* 2^-34 */
real_2expN (&twon34_r, -34);
- twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, TFmode);
- twon34 = force_reg (TFmode, twon34);
+ twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, XFmode);
+ twon34 = force_reg (XFmode, twon34);
- emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34));
+ emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
- emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
+ emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx));
emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
DONE;
})
@@ -2012,7 +1996,7 @@
[(set (match_operand:SI 0 "register_operand" "")
(umod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
+ "TARGET_INLINE_INT_DIV"
{
rtx op2_neg, op1_di, div;
@@ -2032,45 +2016,45 @@
})
(define_insn_and_split "divsi3_internal"
- [(set (match_operand:TF 0 "fr_register_operand" "=&f")
- (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
- (match_operand:TF 2 "fr_register_operand" "f"))))
- (clobber (match_scratch:TF 4 "=&f"))
- (clobber (match_scratch:TF 5 "=&f"))
+ [(set (match_operand:XF 0 "fr_register_operand" "=&f")
+ (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
+ (match_operand:XF 2 "fr_register_operand" "f"))))
+ (clobber (match_scratch:XF 4 "=&f"))
+ (clobber (match_scratch:XF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))
- (use (match_operand:TF 3 "fr_register_operand" "f"))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
+ (use (match_operand:XF 3 "fr_register_operand" "f"))]
+ "TARGET_INLINE_INT_DIV"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
+ [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
(set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 6) (const_int 0))
- (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
+ (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 5)
- (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
+ (plus:XF (neg:XF (mult:XF (match_dup 2) (match_dup 0)))
(match_dup 7)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 4)
- (plus:TF (mult:TF (match_dup 5) (match_dup 4))
+ (plus:XF (mult:XF (match_dup 5) (match_dup 4))
(match_dup 4)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 5)
- (plus:TF (mult:TF (match_dup 5) (match_dup 5))
+ (plus:XF (mult:XF (match_dup 5) (match_dup 5))
(match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 0)
- (plus:TF (mult:TF (match_dup 5) (match_dup 4))
+ (plus:XF (mult:XF (match_dup 5) (match_dup 4))
(match_dup 4)))
(use (const_int 1))]))
]
- "operands[7] = CONST1_RTX (TFmode);"
+ "operands[7] = CONST1_RTX (XFmode);"
[(set_attr "predicable" "no")])
;; ::::::::::::::::::::
@@ -2311,19 +2295,18 @@
operands[4] = gen_reg_rtx (DImode);
})
-;; ??? Ought to invent some unspecs for !INTEL_EXTENDED_IEEE_FORMAT.
;; Note the computation here is op0 = 63 - (exp - 0xffff).
(define_expand "clzdi2"
[(set (match_dup 2)
- (unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "")))
+ (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "")))
(set (match_dup 3)
(unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP))
(set (match_dup 4) (const_int 65598))
(set (match_operand:DI 0 "gr_register_operand" "")
(minus:DI (match_dup 4) (match_dup 3)))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ ""
{
- operands[2] = gen_reg_rtx (TFmode);
+ operands[2] = gen_reg_rtx (XFmode);
operands[3] = gen_reg_rtx (DImode);
operands[4] = gen_reg_rtx (DImode);
})
@@ -2335,11 +2318,11 @@
"popcnt %0 = %1"
[(set_attr "itanium_class" "mmmul")])
-(define_insn "*getf_exp_tf"
+(define_insn "*getf_exp_xf"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
- (unspec:DI [(match_operand:TF 1 "fr_register_operand" "f")]
+ (unspec:DI [(match_operand:XF 1 "fr_register_operand" "f")]
UNSPEC_GETF_EXP))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ ""
"getf.exp %0 = %1"
[(set_attr "itanium_class" "frfr")])
@@ -2347,28 +2330,28 @@
[(set (match_operand:DI 0 "register_operand" "")
(div:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
+ "TARGET_INLINE_INT_DIV"
{
- rtx op1_tf, op2_tf, op0_tf;
+ rtx op1_xf, op2_xf, op0_xf;
- op0_tf = gen_reg_rtx (TFmode);
+ op0_xf = gen_reg_rtx (XFmode);
if (CONSTANT_P (operands[1]))
operands[1] = force_reg (DImode, operands[1]);
- op1_tf = gen_reg_rtx (TFmode);
- expand_float (op1_tf, operands[1], 0);
+ op1_xf = gen_reg_rtx (XFmode);
+ expand_float (op1_xf, operands[1], 0);
if (CONSTANT_P (operands[2]))
operands[2] = force_reg (DImode, operands[2]);
- op2_tf = gen_reg_rtx (TFmode);
- expand_float (op2_tf, operands[2], 0);
+ op2_xf = gen_reg_rtx (XFmode);
+ expand_float (op2_xf, operands[2], 0);
if (TARGET_INLINE_INT_DIV_LAT)
- emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
+ emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf));
else
- emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
+ emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf));
- emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
+ emit_insn (gen_fix_truncxfdi2_alts (operands[0], op0_xf, const1_rtx));
DONE;
})
@@ -2376,7 +2359,7 @@
[(set (match_operand:DI 0 "register_operand" "")
(mod:SI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
+ "TARGET_INLINE_INT_DIV"
{
rtx op2_neg, div;
@@ -2393,28 +2376,28 @@
[(set (match_operand:DI 0 "register_operand" "")
(udiv:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
+ "TARGET_INLINE_INT_DIV"
{
- rtx op1_tf, op2_tf, op0_tf;
+ rtx op1_xf, op2_xf, op0_xf;
- op0_tf = gen_reg_rtx (TFmode);
+ op0_xf = gen_reg_rtx (XFmode);
if (CONSTANT_P (operands[1]))
operands[1] = force_reg (DImode, operands[1]);
- op1_tf = gen_reg_rtx (TFmode);
- expand_float (op1_tf, operands[1], 1);
+ op1_xf = gen_reg_rtx (XFmode);
+ expand_float (op1_xf, operands[1], 1);
if (CONSTANT_P (operands[2]))
operands[2] = force_reg (DImode, operands[2]);
- op2_tf = gen_reg_rtx (TFmode);
- expand_float (op2_tf, operands[2], 1);
+ op2_xf = gen_reg_rtx (XFmode);
+ expand_float (op2_xf, operands[2], 1);
if (TARGET_INLINE_INT_DIV_LAT)
- emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
+ emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf));
else
- emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
+ emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf));
- emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
+ emit_insn (gen_fixuns_truncxfdi2_alts (operands[0], op0_xf, const1_rtx));
DONE;
})
@@ -2422,7 +2405,7 @@
[(set (match_operand:DI 0 "register_operand" "")
(umod:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
+ "TARGET_INLINE_INT_DIV"
{
rtx op2_neg, div;
@@ -2436,112 +2419,112 @@
})
(define_insn_and_split "divdi3_internal_lat"
- [(set (match_operand:TF 0 "fr_register_operand" "=&f")
- (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
- (match_operand:TF 2 "fr_register_operand" "f"))))
- (clobber (match_scratch:TF 3 "=&f"))
- (clobber (match_scratch:TF 4 "=&f"))
- (clobber (match_scratch:TF 5 "=&f"))
+ [(set (match_operand:XF 0 "fr_register_operand" "=&f")
+ (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
+ (match_operand:XF 2 "fr_register_operand" "f"))))
+ (clobber (match_scratch:XF 3 "=&f"))
+ (clobber (match_scratch:XF 4 "=&f"))
+ (clobber (match_scratch:XF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV_LAT"
+ "TARGET_INLINE_INT_DIV_LAT"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
+ [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
(set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
+ (plus:XF (neg:XF (mult:XF (match_dup 2) (match_dup 0)))
(match_dup 7)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
- (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
+ (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
- (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3)))
+ (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 4)
- (plus:TF (mult:TF (match_dup 3) (match_dup 4))
+ (plus:XF (mult:XF (match_dup 3) (match_dup 4))
(match_dup 4)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 0)
- (plus:TF (mult:TF (match_dup 3) (match_dup 0))
+ (plus:XF (mult:XF (match_dup 3) (match_dup 0))
(match_dup 0)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (mult:TF (match_dup 5) (match_dup 4))
+ (plus:XF (mult:XF (match_dup 5) (match_dup 4))
(match_dup 4)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 0)
- (plus:TF (mult:TF (match_dup 5) (match_dup 0))
+ (plus:XF (mult:XF (match_dup 5) (match_dup 0))
(match_dup 0)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 4)
- (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
+ (plus:XF (neg:XF (mult:XF (match_dup 2) (match_dup 3)))
(match_dup 1)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 0)
- (plus:TF (mult:TF (match_dup 4) (match_dup 0))
+ (plus:XF (mult:XF (match_dup 4) (match_dup 0))
(match_dup 3)))
(use (const_int 1))]))
]
- "operands[7] = CONST1_RTX (TFmode);"
+ "operands[7] = CONST1_RTX (XFmode);"
[(set_attr "predicable" "no")])
(define_insn_and_split "divdi3_internal_thr"
- [(set (match_operand:TF 0 "fr_register_operand" "=&f")
- (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
- (match_operand:TF 2 "fr_register_operand" "f"))))
- (clobber (match_scratch:TF 3 "=&f"))
- (clobber (match_scratch:TF 4 "=f"))
+ [(set (match_operand:XF 0 "fr_register_operand" "=&f")
+ (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
+ (match_operand:XF 2 "fr_register_operand" "f"))))
+ (clobber (match_scratch:XF 3 "=&f"))
+ (clobber (match_scratch:XF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV_THR"
+ "TARGET_INLINE_INT_DIV_THR"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
+ [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
(set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
+ (plus:XF (neg:XF (mult:XF (match_dup 2) (match_dup 0)))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 0)
- (plus:TF (mult:TF (match_dup 3) (match_dup 0))
+ (plus:XF (mult:XF (match_dup 3) (match_dup 0))
(match_dup 0)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
- (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3)))
+ (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 0)
- (plus:TF (mult:TF (match_dup 3) (match_dup 0))
+ (plus:XF (mult:XF (match_dup 3) (match_dup 0))
(match_dup 0)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
- (parallel [(set (match_dup 3) (mult:TF (match_dup 0) (match_dup 1)))
+ (parallel [(set (match_dup 3) (mult:XF (match_dup 0) (match_dup 1)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 4)
- (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
+ (plus:XF (neg:XF (mult:XF (match_dup 2) (match_dup 3)))
(match_dup 1)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 0)
- (plus:TF (mult:TF (match_dup 4) (match_dup 0))
+ (plus:XF (mult:XF (match_dup 4) (match_dup 0))
(match_dup 3)))
(use (const_int 1))]))
]
- "operands[6] = CONST1_RTX (TFmode);"
+ "operands[6] = CONST1_RTX (XFmode);"
[(set_attr "predicable" "no")])
;; ::::::::::::::::::::
@@ -2653,7 +2636,7 @@
[(set (match_operand:SF 0 "fr_register_operand" "")
(div:SF (match_operand:SF 1 "fr_register_operand" "")
(match_operand:SF 2 "fr_register_operand" "")))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
+ "TARGET_INLINE_FLOAT_DIV"
{
rtx insn;
if (TARGET_INLINE_FLOAT_DIV_LAT)
@@ -2668,44 +2651,44 @@
[(set (match_operand:SF 0 "fr_register_operand" "=&f")
(div:SF (match_operand:SF 1 "fr_register_operand" "f")
(match_operand:SF 2 "fr_register_operand" "f")))
- (clobber (match_scratch:TF 3 "=&f"))
- (clobber (match_scratch:TF 4 "=f"))
+ (clobber (match_scratch:XF 3 "=&f"))
+ (clobber (match_scratch:XF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
+ "TARGET_INLINE_FLOAT_DIV_LAT"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
+ [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0))
- (parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6)))
+ (parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 4)
- (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
+ (plus:XF (neg:XF (mult:XF (match_dup 8) (match_dup 6)))
(match_dup 10)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (mult:TF (match_dup 4) (match_dup 3))
+ (plus:XF (mult:XF (match_dup 4) (match_dup 3))
(match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
- (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4)))
+ (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (mult:TF (match_dup 4) (match_dup 3))
+ (plus:XF (mult:XF (match_dup 4) (match_dup 3))
(match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
- (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4)))
+ (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 9)
(float_truncate:DF
- (plus:TF (mult:TF (match_dup 4) (match_dup 3))
+ (plus:XF (mult:XF (match_dup 4) (match_dup 3))
(match_dup 3))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
@@ -2713,11 +2696,11 @@
(float_truncate:SF (match_dup 6))))
]
{
- operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
- operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
- operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
+ operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
+ operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
+ operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
- operands[10] = CONST1_RTX (TFmode);
+ operands[10] = CONST1_RTX (XFmode);
}
[(set_attr "predicable" "no")])
@@ -2725,53 +2708,53 @@
[(set (match_operand:SF 0 "fr_register_operand" "=&f")
(div:SF (match_operand:SF 1 "fr_register_operand" "f")
(match_operand:SF 2 "fr_register_operand" "f")))
- (clobber (match_scratch:TF 3 "=&f"))
- (clobber (match_scratch:TF 4 "=f"))
+ (clobber (match_scratch:XF 3 "=&f"))
+ (clobber (match_scratch:XF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
+ "TARGET_INLINE_FLOAT_DIV_THR"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
+ [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
+ (plus:XF (neg:XF (mult:XF (match_dup 8) (match_dup 6)))
(match_dup 10)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (mult:TF (match_dup 3) (match_dup 3))
+ (plus:XF (mult:XF (match_dup 3) (match_dup 3))
(match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 6)
- (plus:TF (mult:TF (match_dup 3) (match_dup 6))
+ (plus:XF (mult:XF (match_dup 3) (match_dup 6))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 9)
(float_truncate:SF
- (mult:TF (match_dup 7) (match_dup 6))))
+ (mult:XF (match_dup 7) (match_dup 6))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 4)
- (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 3)))
+ (plus:XF (neg:XF (mult:XF (match_dup 8) (match_dup 3)))
(match_dup 7)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(set (match_dup 0)
(float_truncate:SF
- (plus:TF (mult:TF (match_dup 4) (match_dup 6))
+ (plus:XF (mult:XF (match_dup 4) (match_dup 6))
(match_dup 3)))))
]
{
- operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
- operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
- operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
+ operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
+ operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
+ operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
- operands[10] = CONST1_RTX (TFmode);
+ operands[10] = CONST1_RTX (XFmode);
}
[(set_attr "predicable" "no")])
@@ -2962,7 +2945,7 @@
[(set (match_operand:DF 0 "fr_register_operand" "")
(div:DF (match_operand:DF 1 "fr_register_operand" "")
(match_operand:DF 2 "fr_register_operand" "")))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
+ "TARGET_INLINE_FLOAT_DIV"
{
rtx insn;
if (TARGET_INLINE_FLOAT_DIV_LAT)
@@ -2977,80 +2960,80 @@
[(set (match_operand:DF 0 "fr_register_operand" "=&f")
(div:DF (match_operand:DF 1 "fr_register_operand" "f")
(match_operand:DF 2 "fr_register_operand" "f")))
- (clobber (match_scratch:TF 3 "=&f"))
- (clobber (match_scratch:TF 4 "=&f"))
- (clobber (match_scratch:TF 5 "=&f"))
+ (clobber (match_scratch:XF 3 "=&f"))
+ (clobber (match_scratch:XF 4 "=&f"))
+ (clobber (match_scratch:XF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
+ "TARGET_INLINE_FLOAT_DIV_LAT"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
+ [(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9)))
(set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 6) (const_int 0))
- (parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7)))
+ (parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 4)
- (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 7)))
+ (plus:XF (neg:XF (mult:XF (match_dup 9) (match_dup 7)))
(match_dup 12)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (mult:TF (match_dup 4) (match_dup 3))
+ (plus:XF (mult:XF (match_dup 4) (match_dup 3))
(match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
- (parallel [(set (match_dup 5) (mult:TF (match_dup 4) (match_dup 4)))
+ (parallel [(set (match_dup 5) (mult:XF (match_dup 4) (match_dup 4)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 7)
- (plus:TF (mult:TF (match_dup 4) (match_dup 7))
+ (plus:XF (mult:XF (match_dup 4) (match_dup 7))
(match_dup 7)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (mult:TF (match_dup 5) (match_dup 3))
+ (plus:XF (mult:XF (match_dup 5) (match_dup 3))
(match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
- (parallel [(set (match_dup 4) (mult:TF (match_dup 5) (match_dup 5)))
+ (parallel [(set (match_dup 4) (mult:XF (match_dup 5) (match_dup 5)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 7)
- (plus:TF (mult:TF (match_dup 5) (match_dup 7))
+ (plus:XF (mult:XF (match_dup 5) (match_dup 7))
(match_dup 7)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 10)
(float_truncate:DF
- (plus:TF (mult:TF (match_dup 4) (match_dup 3))
+ (plus:XF (mult:XF (match_dup 4) (match_dup 3))
(match_dup 3))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 7)
- (plus:TF (mult:TF (match_dup 4) (match_dup 7))
+ (plus:XF (mult:XF (match_dup 4) (match_dup 7))
(match_dup 7)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 11)
(float_truncate:DF
- (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 3)))
+ (plus:XF (neg:XF (mult:XF (match_dup 9) (match_dup 3)))
(match_dup 8))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 6) (const_int 0))
(set (match_dup 0)
- (float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7))
+ (float_truncate:DF (plus:XF (mult:XF (match_dup 5) (match_dup 7))
(match_dup 3)))))
]
{
- operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0]));
- operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1]));
- operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2]));
+ operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0]));
+ operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1]));
+ operands[9] = gen_rtx_REG (XFmode, REGNO (operands[2]));
operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3]));
operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5]));
- operands[12] = CONST1_RTX (TFmode);
+ operands[12] = CONST1_RTX (XFmode);
}
[(set_attr "predicable" "no")])
@@ -3058,48 +3041,48 @@
[(set (match_operand:DF 0 "fr_register_operand" "=&f")
(div:DF (match_operand:DF 1 "fr_register_operand" "f")
(match_operand:DF 2 "fr_register_operand" "f")))
- (clobber (match_scratch:TF 3 "=&f"))
+ (clobber (match_scratch:XF 3 "=&f"))
(clobber (match_scratch:DF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
+ "TARGET_INLINE_FLOAT_DIV_THR"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
+ [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
+ (plus:XF (neg:XF (mult:XF (match_dup 8) (match_dup 6)))
(match_dup 10)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 6)
- (plus:TF (mult:TF (match_dup 3) (match_dup 6))
+ (plus:XF (mult:XF (match_dup 3) (match_dup 6))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
- (mult:TF (match_dup 3) (match_dup 3)))
+ (mult:XF (match_dup 3) (match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 6)
- (plus:TF (mult:TF (match_dup 3) (match_dup 6))
+ (plus:XF (mult:XF (match_dup 3) (match_dup 6))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
- (mult:TF (match_dup 3) (match_dup 3)))
+ (mult:XF (match_dup 3) (match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 6)
- (plus:TF (mult:TF (match_dup 3) (match_dup 6))
+ (plus:XF (mult:XF (match_dup 3) (match_dup 6))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 9)
(float_truncate:DF
- (mult:TF (match_dup 7) (match_dup 3))))
+ (mult:XF (match_dup 7) (match_dup 3))))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 4)
@@ -3112,11 +3095,11 @@
(match_dup 9))))
]
{
- operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
- operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
- operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
+ operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0]));
+ operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1]));
+ operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2]));
operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
- operands[10] = CONST1_RTX (TFmode);
+ operands[10] = CONST1_RTX (XFmode);
}
[(set_attr "predicable" "no")])
@@ -3126,499 +3109,499 @@
;; ::
;; ::::::::::::::::::::
-(define_insn "addtf3"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "addxf3"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
+ ""
"fadd %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*addtf3_truncsf"
+(define_insn "*addxf3_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
- (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
+ ""
"fadd.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*addtf3_truncdf"
+(define_insn "*addxf3_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF
- (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
+ ""
"fadd.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
-(define_insn "subtf3"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "subxf3"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
+ ""
"fsub %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*subtf3_truncsf"
+(define_insn "*subxf3_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
- (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
+ ""
"fsub.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*subtf3_truncdf"
+(define_insn "*subxf3_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF
- (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
+ ""
"fsub.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
-(define_insn "multf3"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "mulxf3"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
+ ""
"fmpy %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*multf3_truncsf"
+(define_insn "*mulxf3_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
- (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
+ ""
"fmpy.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*multf3_truncdf"
+(define_insn "*mulxf3_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF
- (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
+ ""
"fmpy.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*multf3_alts"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
+(define_insn "*mulxf3_alts"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 3 "const_int_operand" ""))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ ""
"fmpy.s%3 %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*multf3_truncsf_alts"
+(define_insn "*mulxf3_truncsf_alts"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
- (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
+ (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 3 "const_int_operand" ""))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ ""
"fmpy.s.s%3 %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*multf3_truncdf_alts"
+(define_insn "*mulxf3_truncdf_alts"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF
- (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
+ (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 3 "const_int_operand" ""))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ ""
"fmpy.d.s%3 %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
-(define_insn "abstf2"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "absxf2"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))]
+ ""
"fabs %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
-(define_insn "negtf2"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "negxf2"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))]
+ ""
"fneg %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
-(define_insn "*nabstf2"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "*nabsxf2"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))]
+ ""
"fnegabs %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
-(define_insn "mintf3"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "minxf3"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
+ ""
"fmin %0 = %F1, %F2"
[(set_attr "itanium_class" "fmisc")])
-(define_insn "maxtf3"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "maxxf3"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
+ ""
"fmax %0 = %F1, %F2"
[(set_attr "itanium_class" "fmisc")])
-(define_insn "*maddtf4"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
- (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "*maddxf4"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
+ ""
"fma %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*maddtf4_truncsf"
+(define_insn "*maddxf4_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
- (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
- (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
+ ""
"fma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*maddtf4_truncdf"
+(define_insn "*maddxf4_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF
- (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
- (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
+ ""
"fma.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*maddtf4_alts"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
- (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
+(define_insn "*maddxf4_alts"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 4 "const_int_operand" ""))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ ""
"fma.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*maddtf4_alts_truncdf"
+(define_insn "*maddxf4_alts_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF
- (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
- (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
+ (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 4 "const_int_operand" ""))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ ""
"fma.d.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*msubtf4"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
- (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "*msubxf4"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
+ ""
"fms %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*msubtf4_truncsf"
+(define_insn "*msubxf4_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
- (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
- (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
+ ""
"fms.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*msubtf4_truncdf"
+(define_insn "*msubxf4_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF
- (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
- (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
+ ""
"fms.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*nmultf3"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "*nmulxf3"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
+ ""
"fnmpy %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*nmultf3_truncsf"
+(define_insn "*nmulxf3_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
- (neg:TF (mult:TF
- (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (neg:XF (mult:XF
+ (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))]
+ ""
"fnmpy.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*nmultf3_truncdf"
+(define_insn "*nmulxf3_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF
- (neg:TF (mult:TF
- (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (neg:XF (mult:XF
+ (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))]
+ ""
"fnmpy.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
-(define_insn "*nmaddtf4"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (plus:TF (neg:TF (mult:TF
- (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
- (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+(define_insn "*nmaddxf4"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (plus:XF (neg:XF (mult:XF
+ (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
+ ""
"fnma %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*nmaddtf4_truncsf"
+(define_insn "*nmaddxf4_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
- (plus:TF (neg:TF (mult:TF
- (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
- (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (plus:XF (neg:XF (mult:XF
+ (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
+ ""
"fnma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*nmaddtf4_truncdf"
+(define_insn "*nmaddxf4_truncdf"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF
- (plus:TF (neg:TF (mult:TF
- (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
- (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (plus:XF (neg:XF (mult:XF
+ (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
+ ""
"fnma.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*nmaddtf4_alts"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (plus:TF (neg:TF (mult:TF
- (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
- (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
+(define_insn "*nmaddxf4_alts"
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (plus:XF (neg:XF (mult:XF
+ (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))
(use (match_operand:SI 4 "const_int_operand" ""))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ ""
"fnma.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
-(define_insn "*nmaddtf4_truncdf_alts"
+(define_insn "*nmaddxf4_truncdf_alts"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(float_truncate:DF
- (plus:TF (neg:TF
- (mult:TF
- (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
- (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
+ (plus:XF (neg:XF
+ (mult:XF
+ (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))
(use (match_operand:SI 4 "const_int_operand" ""))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ ""
"fnma.d.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
-(define_expand "divtf3"
- [(set (match_operand:TF 0 "fr_register_operand" "")
- (div:TF (match_operand:TF 1 "fr_register_operand" "")
- (match_operand:TF 2 "fr_register_operand" "")))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
+(define_expand "divxf3"
+ [(set (match_operand:XF 0 "fr_register_operand" "")
+ (div:XF (match_operand:XF 1 "fr_register_operand" "")
+ (match_operand:XF 2 "fr_register_operand" "")))]
+ "TARGET_INLINE_FLOAT_DIV"
{
rtx insn;
if (TARGET_INLINE_FLOAT_DIV_LAT)
- insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]);
+ insn = gen_divxf3_internal_lat (operands[0], operands[1], operands[2]);
else
- insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]);
+ insn = gen_divxf3_internal_thr (operands[0], operands[1], operands[2]);
emit_insn (insn);
DONE;
})
-(define_insn_and_split "divtf3_internal_lat"
- [(set (match_operand:TF 0 "fr_register_operand" "=&f")
- (div:TF (match_operand:TF 1 "fr_register_operand" "f")
- (match_operand:TF 2 "fr_register_operand" "f")))
- (clobber (match_scratch:TF 3 "=&f"))
- (clobber (match_scratch:TF 4 "=&f"))
- (clobber (match_scratch:TF 5 "=&f"))
- (clobber (match_scratch:TF 6 "=&f"))
+(define_insn_and_split "divxf3_internal_lat"
+ [(set (match_operand:XF 0 "fr_register_operand" "=&f")
+ (div:XF (match_operand:XF 1 "fr_register_operand" "f")
+ (match_operand:XF 2 "fr_register_operand" "f")))
+ (clobber (match_scratch:XF 3 "=&f"))
+ (clobber (match_scratch:XF 4 "=&f"))
+ (clobber (match_scratch:XF 5 "=&f"))
+ (clobber (match_scratch:XF 6 "=&f"))
(clobber (match_scratch:BI 7 "=c"))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
+ "TARGET_INLINE_FLOAT_DIV_LAT"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
+ [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
(set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
+ (plus:XF (neg:XF (mult:XF (match_dup 2) (match_dup 0)))
(match_dup 8)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 7) (const_int 0))
- (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
+ (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 7) (const_int 0))
- (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3)))
+ (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 6)
- (plus:TF (mult:TF (match_dup 3) (match_dup 3))
+ (plus:XF (mult:XF (match_dup 3) (match_dup 3))
(match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (mult:TF (match_dup 5) (match_dup 5))
+ (plus:XF (mult:XF (match_dup 5) (match_dup 5))
(match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 5)
- (plus:TF (mult:TF (match_dup 6) (match_dup 0))
+ (plus:XF (mult:XF (match_dup 6) (match_dup 0))
(match_dup 0)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 0)
- (plus:TF (mult:TF (match_dup 5) (match_dup 3))
+ (plus:XF (mult:XF (match_dup 5) (match_dup 3))
(match_dup 0)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 4)
- (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4)))
+ (plus:XF (neg:XF (mult:XF (match_dup 2) (match_dup 4)))
(match_dup 1)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (mult:TF (match_dup 3) (match_dup 0))
+ (plus:XF (mult:XF (match_dup 3) (match_dup 0))
(match_dup 4)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 5)
- (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
+ (plus:XF (neg:XF (mult:XF (match_dup 2) (match_dup 0)))
(match_dup 8)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 0)
- (plus:TF (mult:TF (match_dup 4) (match_dup 0))
+ (plus:XF (mult:XF (match_dup 4) (match_dup 0))
(match_dup 0)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 4)
- (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
+ (plus:XF (neg:XF (mult:XF (match_dup 2) (match_dup 3)))
(match_dup 1)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 7) (const_int 0))
(set (match_dup 0)
- (plus:TF (mult:TF (match_dup 4) (match_dup 0))
+ (plus:XF (mult:XF (match_dup 4) (match_dup 0))
(match_dup 3))))
]
- "operands[8] = CONST1_RTX (TFmode);"
+ "operands[8] = CONST1_RTX (XFmode);"
[(set_attr "predicable" "no")])
-(define_insn_and_split "divtf3_internal_thr"
- [(set (match_operand:TF 0 "fr_register_operand" "=&f")
- (div:TF (match_operand:TF 1 "fr_register_operand" "f")
- (match_operand:TF 2 "fr_register_operand" "f")))
- (clobber (match_scratch:TF 3 "=&f"))
- (clobber (match_scratch:TF 4 "=&f"))
+(define_insn_and_split "divxf3_internal_thr"
+ [(set (match_operand:XF 0 "fr_register_operand" "=&f")
+ (div:XF (match_operand:XF 1 "fr_register_operand" "f")
+ (match_operand:XF 2 "fr_register_operand" "f")))
+ (clobber (match_scratch:XF 3 "=&f"))
+ (clobber (match_scratch:XF 4 "=&f"))
(clobber (match_scratch:BI 5 "=c"))]
- "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
+ "TARGET_INLINE_FLOAT_DIV_THR"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
+ [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
(set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
+ (plus:XF (neg:XF (mult:XF (match_dup 2) (match_dup 0)))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 4)
- (plus:TF (mult:TF (match_dup 3) (match_dup 0))
+ (plus:XF (mult:XF (match_dup 3) (match_dup 0))
(match_dup 0)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
- (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3)))
+ (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (mult:TF (match_dup 3) (match_dup 4))
+ (plus:XF (mult:XF (match_dup 3) (match_dup 4))
(match_dup 4)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
- (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
+ (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 0)
- (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
+ (plus:XF (neg:XF (mult:XF (match_dup 2) (match_dup 3)))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 0)
- (plus:TF (mult:TF (match_dup 0) (match_dup 3))
+ (plus:XF (mult:XF (match_dup 0) (match_dup 3))
(match_dup 3)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4)))
+ (plus:XF (neg:XF (mult:XF (match_dup 2) (match_dup 4)))
(match_dup 1)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
- (plus:TF (mult:TF (match_dup 3) (match_dup 0))
+ (plus:XF (mult:XF (match_dup 3) (match_dup 0))
(match_dup 4)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 4)
- (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
+ (plus:XF (neg:XF (mult:XF (match_dup 2) (match_dup 0)))
(match_dup 6)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 0)
- (plus:TF (mult:TF (match_dup 4) (match_dup 0))
+ (plus:XF (mult:XF (match_dup 4) (match_dup 0))
(match_dup 0)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 4)
- (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
+ (plus:XF (neg:XF (mult:XF (match_dup 2) (match_dup 3)))
(match_dup 1)))
(use (const_int 1))]))
(cond_exec (ne (match_dup 5) (const_int 0))
(set (match_dup 0)
- (plus:TF (mult:TF (match_dup 4) (match_dup 0))
+ (plus:XF (mult:XF (match_dup 4) (match_dup 0))
(match_dup 3))))
]
- "operands[6] = CONST1_RTX (TFmode);"
+ "operands[6] = CONST1_RTX (XFmode);"
[(set_attr "predicable" "no")])
;; ??? frcpa works like cmp.foo.unc.
(define_insn "*recip_approx"
- [(set (match_operand:TF 0 "fr_register_operand" "=f")
- (div:TF (const_int 1)
- (match_operand:TF 3 "fr_register_operand" "f")))
+ [(set (match_operand:XF 0 "fr_register_operand" "=f")
+ (div:XF (const_int 1)
+ (match_operand:XF 3 "fr_register_operand" "f")))
(set (match_operand:BI 1 "register_operand" "=c")
- (unspec:BI [(match_operand:TF 2 "fr_register_operand" "f")
+ (unspec:BI [(match_operand:XF 2 "fr_register_operand" "f")
(match_dup 3)] UNSPEC_FR_RECIP_APPROX))
(use (match_operand:SI 4 "const_int_operand" ""))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ ""
"frcpa.s%4 %0, %1 = %2, %3"
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
@@ -4015,11 +3998,11 @@
DONE;
})
-(define_expand "cmptf"
+(define_expand "cmpxf"
[(set (cc0)
- (compare (match_operand:TF 0 "tfreg_or_fp01_operand" "")
- (match_operand:TF 1 "tfreg_or_fp01_operand" "")))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ (compare (match_operand:XF 0 "xfreg_or_fp01_operand" "")
+ (match_operand:XF 1 "xfreg_or_fp01_operand" "")))]
+ ""
{
ia64_compare_op0 = operands[0];
ia64_compare_op1 = operands[1];
@@ -4086,12 +4069,12 @@
"fcmp.%D1 %0, %I0 = %F2, %F3"
[(set_attr "itanium_class" "fcmp")])
-(define_insn "*cmptf_internal"
+(define_insn "*cmpxf_internal"
[(set (match_operand:BI 0 "register_operand" "=c")
(match_operator:BI 1 "comparison_operator"
- [(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")
- (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))]
- "INTEL_EXTENDED_IEEE_FORMAT"
+ [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))]
+ ""
"fcmp.%D1 %0, %I0 = %F2, %F3"
[(set_attr "itanium_class" "fcmp")])
@@ -5052,16 +5035,16 @@
[(set_attr "itanium_class" "ld")])
(define_insn "fr_spill"
- [(set (match_operand:TF 0 "memory_operand" "=m")
- (unspec:TF [(match_operand:TF 1 "register_operand" "f")]
+ [(set (match_operand:XF 0 "memory_operand" "=m")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "f")]
UNSPEC_FR_SPILL))]
""
"stf.spill %0 = %1%P0"
[(set_attr "itanium_class" "stf")])
(define_insn "fr_restore"
- [(set (match_operand:TF 0 "register_operand" "=f")
- (unspec:TF [(match_operand:TF 1 "memory_operand" "m")]
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 1 "memory_operand" "m")]
UNSPEC_FR_RESTORE))]
""
"ldf.fill %0 = %1%P1"
===================================================================
Index: config/ia64/lib1funcs.asm
--- config/ia64/lib1funcs.asm 6 Jul 2001 00:35:11 -0000 1.15
+++ config/ia64/lib1funcs.asm 16 Oct 2003 22:09:38 -0000
@@ -1,15 +1,19 @@
-#ifdef L__divtf3
+#ifdef L__divxf3
// Compute a 80-bit IEEE double-extended quotient.
//
// From the Intel IA-64 Optimization Guide, choose the minimum latency
// alternative.
//
// farg0 holds the dividend. farg1 holds the divisor.
+//
+// __divtf3 is an alternate symbol name for backward compatibility.
.text
.align 16
+ .global __divxf3
.global __divtf3
- .proc __divtf3
+ .proc __divxf3
+__divxf3:
__divtf3:
cmp.eq p7, p0 = r0, r0
frcpa.s0 f10, p6 = farg0, farg1
@@ -37,7 +41,7 @@ __divtf3:
(p6) fma.s0 fret0 = f12, f10, f11
(p7) mov fret0 = f10
br.ret.sptk rp
- .endp __divtf3
+ .endp __divxf3
#endif
#ifdef L__divdf3
@@ -700,4 +704,40 @@ __ia64_trampoline:
;;
}
.endp __ia64_trampoline
+#endif
+
+#ifdef L__compat
+// Thunks for backward compatibility.
+
+ .text
+ .align 16
+ .global __fixtfti
+ .proc __fixtfti
+__fixtfti:
+ { .bbb
+ br.sptk.many __fixxfti
+ ;;
+ }
+ .endp __fixtfti
+
+ .align 16
+ .global __fixunstfti
+ .proc __fixunstfti
+__fixunstfti:
+ { .bbb
+ br.sptk.many __fixunsxfti
+ ;;
+ }
+ .endp __fixunstfti
+
+ .align 16
+ .global __floattitf
+ .proc __floattitf
+__floattitf:
+ { .bbb
+ br.sptk.many __floattixf
+ ;;
+ }
+ .endp __floattitf
+
#endif
===================================================================
Index: config/ia64/t-ia64
--- config/ia64/t-ia64 4 Jun 2003 17:05:59 -0000 1.19
+++ config/ia64/t-ia64 16 Oct 2003 22:09:38 -0000
@@ -5,10 +5,10 @@ LIB1ASMSRC = ia64/lib1funcs.asm
# we use __ as the prefix. Note that L_divdi3 in libgcc2.c actually defines
# a TImode divide function, so there is no actual overlap here between
# libgcc2.c and lib1funcs.asm.
-LIB1ASMFUNCS = __divtf3 __divdf3 __divsf3 \
+LIB1ASMFUNCS = __divxf3 __divdf3 __divsf3 \
__divdi3 __moddi3 __udivdi3 __umoddi3 \
__divsi3 __modsi3 __udivsi3 __umodsi3 __save_stack_nonlocal \
- __nonlocal_goto __restore_stack_nonlocal __trampoline
+ __nonlocal_goto __restore_stack_nonlocal __trampoline __compat
# ??? Hack to get -P option used when compiling lib1funcs.asm, because Intel
# assembler does not accept # line number as a comment.