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[PATCH] - Use of powerpc 64bit instructions in 32bit ABI

We would like to support use of powerPC's 64bit instructions in Macho-O powerPC's 32bit abi. This is performance gain
for programs which make heavy use of 'long long' data types. 186.crafty has shown good performance gain on the G5
machine. To summarize, the -mpowerpc64 option allows GCC to generate the additional 64-bit instructions that are
found in the full PowerPC64 architecture and to treat GPRs as 64-bit, doubleword quantities (gcc man page). This patch
makes the necessary changes at point of calls, processing of incoming function arguments, function return values and
var-args so 32bit abi does not change. Patch has been tested by bootstrapping gcc and running deja-gnu test suite on

ChangeLog entry:

2003-10-14 Fariborz Jahanian <>

* calls.c: emit_push_insn moved from expr.c and made static.
(load_register_parameters): use of UNITS_PER_REGISTER_ARGUMENT macro.
(store_one_arg): use of UNITS_PER_REGISTER_ARGUMENT macro.
* doloop.c (doloop_optimize): use mode that loop actually iterates in,
instead of word_mode.
* expmed.c (expand_mult_highpart): widen the mode if narrower than
SImode instead of word_mode.
* expr.c: move_block_to_reg and move_block_from_reg moved to function.c.
emit_push_insn moved to calls.c. STACK_GROWS_DOWNWARD,
STACK_PUSH_CODE PRE_INC definitions moved to expr.h. These are done to
make calls.c and function.c self-contained in RTL generation for calls and
function arguments.
STACK_PUSH_CODE PRE_INC definitions moved here and removed from expr.c.
Declaration of move_block_from_reg, move_block_to_reg and emit_push_insn
* function.c (gen_subword_offset): new function used for generating RTLs
for save and restore of arguments in registers.
(operand_subword_offset_force): new function used for generating RTLs
for save and restore of arguments in registers.
(move_block_from_reg, move_block_to_reg): moved here from expr.c
(assign_parms): generate rtl to combine arguments passed in two registers
in a register.
* function.h: added declaration of move_block_from_reg.
* reload.c (find_equiv_reg): Examine DF const to see if we can use
one subword of the 64-bit value. Reg must be two 32-bit registers with DF mode.
* unroll.c (precondition_loop_p): use mode that loop actually iterates in,
instead of word_mode.
* rs6000.c (build_mask64_2_operand): this routine is made to work for 32bit
hosted gcc generating 64bit instructions.
(input_operand): use UNITS_PER_REGISTER_ARGUMENT where UNITS_PER_WORD was used.
(rs6000_emit_set_long_const): fix bug when input arguments are 64bit long in value.
(rs6000_emit_move): use REGISTER_ARGUMENT_MODE instead of word_mode.
(init_cumulative_args): add code to know if a call is a vararg call.
(function_arg): splits up a DFmode or DImode argument in vararg list into zero,
one or two GPRs.
(rs6000_va_start, rs6000_va_arg, rs6000_stack_info,
rs6000_emit_prologue, rs6000_output_function_epilogue): misc changes to use
appropriate macros.
(rs6000_function_value): split DImode return values into two psuedo registers.
* rs6000.h: Definitions of new macros are added here.
* Separate TARGET_POWERPC64 patterns for TARGET_64BIT or TARGET_32BIT.
(ashrdi3_to_si_no_power) Generate more efficient code for 32-bit right-shift of
a "long long" argument.
and REGISTER_ARGUMENT_MODE are explained here.

Attachment: ppc_fsf3dot4_patch.txt
Description: Text document

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