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[MIPS PATCH RFA] support prefx, clean up mips_emit_prefetch.
- From: cgd at broadcom dot com
- To: gcc-patches at gcc dot gnu dot org
- Cc: echristo at redhat dot com
- Date: 03 Oct 2003 13:25:23 -0700
- Subject: [MIPS PATCH RFA] support prefx, clean up mips_emit_prefetch.
This patch adds support for 'prefx' to the MIPS back-end, and cleans
up mips_emit_prefetch. (the cleanups make mips_emit_prefetch a bit
clearer at least to me, and would keep it from going badly wrong if
the meanings of the write or locality prefetch RTL arguments are ever
changed...)
Some things to note:
* I added the new "prefetchx" type attr because I know of processors
(*cough*) where prefetch and prefx schedule differently. (Same with
FP loads and FP indexed loads; maybe I'll making a new FP load
indexed type eventually, or somebody else will beat me to it...)
* nothing currently does anything special when the type attr is
"prefetch," so AFAIK I didn't have to do update anything for
prefetchx either. (i.e., no DFAs used "prefetch", so i wasn't
include to make them use "prefetchx".)
* ISA_HAS_PREFETCHX: technically, mips32r2 w/ 64-bit FPU supports
prefx (and other instructions, e.g. those controlled by
ISA_HAS_FP4). Since misp32r2 w/ 64-bit FPU isn't supported in
general (e.g. for the other ops), I didn't feel inclined to do
something special w/ ISA_HAS_PREFETCHX.
tested w/ mipsisa64-elf on simulator, -mips32 and -mips64 multilibs.
Tested C and C++, no regressions. (-mips32 multilib initially had
trouble because i botched the conditions for use of prefx, but all
fixed now. 8-).
chris
--
2003-10-03 Chris Demetriou <cgd@broadcom.com>
* config/mips/mips.c (mips_emit_prefetch): Restructure
to avoid use of arrays, handle indexed prefetch.
* config/mips/mips.h (ISA_HAS_FP4, ISA_HAS_PREFETCH): Update comments.
(ISA_HAS_PREFETCHX): New deffine.
* config/mips/mips.md ("type" attr): Add new "prefetchx" value,
update comments.
(prefetch_indexed_di, prefetch_indexed_si): New insns.
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.319
diff -u -p -r1.319 mips.c
--- config/mips/mips.c 2 Oct 2003 23:45:04 -0000 1.319
+++ config/mips/mips.c 3 Oct 2003 20:15:01 -0000
@@ -9633,30 +9633,22 @@ mips_use_dfa_pipeline_interface (void)
const char *
mips_emit_prefetch (rtx *operands)
{
- /* For the mips32/64 architectures the hint fields are arranged
- by operation (load/store) and locality (normal/streamed/retained).
- Irritatingly, numbers 2 and 3 are reserved leaving no simple
- algorithm for figuring the hint. */
-
int write = INTVAL (operands[1]);
int locality = INTVAL (operands[2]);
+ int indexed = GET_CODE (operands[3]) == REG;
+ int code;
+ char buffer[30];
+
+ if (locality <= 0)
+ code = (write ? 5 : 4); /* store_streamed / load_streamed. */
+ else if (locality <= 2)
+ code = (write ? 1 : 0); /* store / load. */
+ else
+ code = (write ? 7 : 6); /* store_retained / load_retained. */
- static const char * const alt[2][4] = {
- {
- "pref\t4,%3(%0)",
- "pref\t0,%3(%0)",
- "pref\t0,%3(%0)",
- "pref\t6,%3(%0)"
- },
- {
- "pref\t5,%3(%0)",
- "pref\t1,%3(%0)",
- "pref\t1,%3(%0)",
- "pref\t7,%3(%0)"
- }
- };
-
- return alt[write][locality];
+ sprintf (buffer, "%s\t%d,%%3(%%0)", indexed ? "prefx" : "pref", code);
+ output_asm_insn (buffer, operands);
+ return "";
}
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.292
diff -u -p -r1.292 mips.h
--- config/mips/mips.h 2 Oct 2003 00:44:24 -0000 1.292
+++ config/mips/mips.h 3 Oct 2003 20:15:01 -0000
@@ -823,9 +823,9 @@ extern const struct mips_cpu_info *mips_
|| ISA_MIPS32R2 \
|| ISA_MIPS64)
-/* This is a catch all for the other new mips4 instructions: indexed load and
- indexed prefetch instructions, the FP madd and msub instructions,
- and the FP recip and recip sqrt instructions */
+/* This is a catch all for other mips4 instructions: indexed load, the
+ FP madd and msub instructions, and the FP recip and recip sqrt
+ instructions. */
#define ISA_HAS_FP4 ((ISA_MIPS4 \
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
@@ -901,12 +901,20 @@ extern const struct mips_cpu_info *mips_
|| TARGET_SR71K \
))
-/* ISA has data prefetch instruction. */
+/* ISA has data prefetch instructions. This controls use of 'pref'. */
#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
+
+/* ISA has data indexed prefetch instructions. This controls use of
+ 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
+ (prefx is a cop1x instruction, so can only be used if FP is
+ enabled.) */
+#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
+ || ISA_MIPS64) \
+ && !TARGET_MIPS16)
/* True if trunc.w.s and trunc.w.d are real (not synthetic)
instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.197
diff -u -p -r1.197 mips.md
--- config/mips/mips.md 2 Oct 2003 23:45:05 -0000 1.197
+++ config/mips/mips.md 3 Oct 2003 20:15:02 -0000
@@ -98,7 +98,8 @@
;; call unconditional call
;; load load instruction(s)
;; store store instruction(s)
-;; prefetch memory prefetch
+;; prefetch memory prefetch (register + offset)
+;; prefetchx memory indexed prefetch (register + register)
;; move data movement within same register set
;; condmove conditional moves
;; xfer transfer to/from coprocessor
@@ -123,7 +124,7 @@
;; multi multiword sequence (or user asm statements)
;; nop no operation
(define_attr "type"
- "unknown,branch,jump,call,load,store,prefetch,move,condmove,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
+ "unknown,branch,jump,call,load,store,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
(cond [(eq_attr "jal" "!unset")
(const_string "call")]
(const_string "unknown")))
@@ -8513,6 +8514,15 @@ ld\t%2,%1-%S1(%2)\;daddu\t%2,%2,$31\;%*j
{ return mips_emit_prefetch (operands); }
[(set_attr "type" "prefetch")])
+(define_insn "prefetch_indexed_si"
+ [(prefetch (plus:SI (match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "r"))
+ (match_operand:SI 1 "const_int_operand" "n")
+ (match_operand:SI 2 "const_int_operand" "n"))]
+ "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && Pmode == SImode"
+ { return mips_emit_prefetch (operands); }
+ [(set_attr "type" "prefetchx")])
+
(define_insn "prefetch_si"
[(prefetch (match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "const_int_operand" "n")
@@ -8532,6 +8542,15 @@ ld\t%2,%1-%S1(%2)\;daddu\t%2,%2,$31\;%*j
"ISA_HAS_PREFETCH && Pmode == DImode"
{ return mips_emit_prefetch (operands); }
[(set_attr "type" "prefetch")])
+
+(define_insn "prefetch_indexed_di"
+ [(prefetch (plus:DI (match_operand:DI 0 "register_operand" "r")
+ (match_operand:DI 3 "register_operand" "r"))
+ (match_operand:DI 1 "const_int_operand" "n")
+ (match_operand:DI 2 "const_int_operand" "n"))]
+ "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && Pmode == DImode"
+ { return mips_emit_prefetch (operands); }
+ [(set_attr "type" "prefetchx")])
(define_insn "prefetch_di"
[(prefetch (match_operand:DI 0 "register_operand" "r")