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[patch] backends.html: New. (Take 5)
Hi,
Here is a take 5 in html. I renamed the file to backends.html and
picked style.mhtml as a parent as suggested by Janis.
I personally tried flipping every characteristic, which still made the
table dense. Then I tried flipping ones where the character appears
more often than not, but I found a problem.
L Integer registers are at least 32 bits wide.
Q Integer registers are at least 64 bits wide.
L appears often, but not Q, so if I take the latter method, L gets
flipped, but not Q. That is,
L Integer registers are *narrower* than 32 bits.
Q Integer registers are at least than 64 bits.
This is ugly. I guess we can put off this issue after the file is
committed. The version below is an un-flipped one.
Kazu Hirata
Index: style.mhtml
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/style.mhtml,v
retrieving revision 1.65
diff -u -r1.65 style.mhtml
--- style.mhtml 17 Aug 2003 22:59:18 -0000 1.65
+++ style.mhtml 2 Oct 2003 19:18:55 -0000
@@ -219,7 +219,8 @@
<a href="<get-var BACKPATH>contributewhy.html">...Why?</a><br />
<a href="<get-var BACKPATH>projects/">Open projects</a><br />
<a href="<get-var BACKPATH>frontends.html">Front ends</a><br />
+ <a href="<get-var BACKPATH>backends.html">Back ends</a><br />
<a href="<get-var BACKPATH>extensions.html">Extensions</a><br />
<a href="<get-var BACKPATH>cvs.html">CVS read access</a><br />
<a href="<get-var BACKPATH>rsync.html">Rsync read access</a><br />
--- /dev/null 2003-01-30 05:24:37.000000000 -0500
+++ backends.html 2003-10-02 15:11:27.000000000 -0400
@@ -0,0 +1,112 @@
+<html>
+
+<head>
+<title>Status of Supported Architectures from Maintainers' Point of View</title>
+</head>
+
+<body>
+<h1>Status of Supported Architectures from Maintainers' Point of View</h1>
+
+<p>The table below contains different characteristics for all
+architectures supported by GCC and is intended to alleviate the task
+of maintaining the list of obsoleted targets by having various GCC
+maintainers update this page themselves. Each characteristic has a
+unique letter. In all cases, a question mark means the author didn't
+know whether the architecture had the characteristic or not as of
+writing.</p>
+
+<p>Characteristics describing fundamental properties of the
+architecture or target use CAPITAL LETTERS; characteristics describing
+properties of the GCC port to that architecture or target use small
+letters. In each characteristic, the more common case uses a space
+for the table to look not as dense.</p>
+
+<p>Architectures are identified by their gcc/config subdirectory,
+*not* their CPU field in config.guess output.</p>
+
+<pre>
+Architecture characteristic key
+-----------------------------------------------------------------------
+H A hardware implementation exists.
+M A hardware implementation is currently being manufactured.
+S A Free simulator exists.
+L Integer registers are at least 32 bits wide.
+Q Integer registers are at least 64 bits wide.
+N Memory is byte addressable and bytes are eight bits.
+F Floating point arithmetic is supported
+ (not necessarily by all implementations)
+I IEEE floating point is supported
+ (possibly with software assistance for full conformance)
+C Architecture does not have a single condition code register.
+B Architecture does not have delay slots.
+D Architecture has a stack that grows downward.
+
+l Port can use ILP32 mode integer arithmetic.
+q Port can use LP64 mode integer arithmetic.
+r Port can switch between ILP32 and LP64 at runtime.
+ (Not necessarily supported by all subtargets.)
+c Port does not use cc0.
+p Port does not use define_peephole.
+f Port defines prologue and/or epilogue RTL expanders.
+g Port does not define TARGET_ASM_FUNCTION_(PRO|EPI)LOGUE.
+m Port uses define_constants.
+b Port does not use '"* ..."' notation for output template code.
+d Port uses DFA scheduler descriptions.
+h Port does not contain old scheduler descriptions.
+a Port generates multiple inheritance thunks using
+ TARGET_ASM_OUTPUT_MI(_VCALL)_THUNK.
+t All insns either produce exactly one assembly instruction, or
+ trigger a define_split.
+e <arch>-elf is a supported target.
+s <arch>-elf is the correct target to use with the simulator
+ in /cvs/src.
+</pre>
+
+<pre>
+ | Characteristics
+Target | HMSLQNFICBD lqrcpfgmbdhates
+---------+----------------------------
+alpha | H??LQNFICBD lq cpfgmbdha
+arc | ???L N D l cp e
+arm | HMSL NFI BD l c f m dha es
+avr | HMS N BD h e
+c4x | H??L F l c fgm t
+cris | HM L N I D l ha e
+d30v | ??SL N CBD l cpf es
+dsp16xx | ??? B
+fr30 | ??SL N D l c fg h tes
+frv | ??SL NFI D l cpf m dha es
+h8300 | HMSL N BD l pf m h es
+i370 | H ?L NF B l p h
+i386 | HM?LQNFI BD lq cpf m d a e
+i860 | H ?L NFI BD l p m h
+i960 | H SL NFI B l c a
+ia64 | HM?LQNFICBD lqrcpf m dha e
+ip2k | ??? N BD b h e
+iq2000 | ???L N C D l cpfgm te
+m32r | ??SL N BD l c f es
+m68hc11 | HMS N BD f m h tes
+m68k | HM?L NFI BD l m ha e
+mcore | H?SL N BD l c fg es
+mips | HMSLQNFIC D lqrc f mbd es
+mmix | SLQNFICBD lq cpf mb ha
+mn10300 | ??SL NFI BD l fgm h es
+ns32k | H ?L NFI BD l h
+pa | HM?LQNFIC lqrc f dha
+pdp11 | HMS NF BD l r p h
+rs6000 | HMSLQNFI BD lqrc f m dha e
+s390 | HM?LQNFI BD lqrcpfgmbd a
+sh | HMSLQNFIC D lqrc f m d a e
+sparc | HMSLQNFIC D lqrc f mbdha e
+stormy16 | ??? N CB cpf hate
+v850 | ??SL N BD l pfg es
+vax | H ?L NF BD l pf m ha
+xtensa | HM?L NFICBD l cpf mb e
+</pre>
+
+<p>For AVR simulator, see <a
+href="http://gcc.gnu.org/ml/gcc/2003-10/msg00027.html";
+http://gcc.gnu.org/ml/gcc/2003-10/msg00027.html";</a>.</p>
+
+</body>
+</html>