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RFA: patch to fr500 scheduler
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: 02 Oct 2003 14:22:33 +0100
- Subject: RFA: patch to fr500 scheduler
This patch is an attempt to tidy up the fr500 scheduler a bit.
It's preparing for a general scheduling change that I'm hoping
to submit soon.
Several assorted things:
- Remove the "m7" type and associated insn reservation.
-> No instruction uses m7 and I can't find it mentioned in the
fr500 manual. ISTR the scheduler was written to very early
documentation, so it's possible that the classifications were
changed later on.
- Remove various placeholder insn reservations.
- Combine some insn reservations that had the same behaviour.
- Add new fscmp and fdcmp insn types. Change their latency from
3 to 4 cycles.
- Split out some units which modeled fr500-specific restrictions.
Prefix them with "fr500_" and put them into new automota.
- Prefix all the fr500 insn reservations with "fr500_".
Also, there was some confusion with the "fmas" insn type:
- There is actually an FR-V "fmas" instruction, which gcc doesn't use,
but which is available on the fr500. Based on the insn reservation
name ("f5"), it looks like this was what the scheduler was catering for.
- The insn patterns were using the "fmas" type for multiply-accumulate
instructions. These are defined in the generic FR-V ISA but aren't
(AFAIK) implemented by any real processor. We still use them for
-mcpu=frv (an idealised machine), but it seems better to treat them
like other multiplication instructions.
So, the patch removes the "fmas" type and replaces it with "fsmadd"
and "fdmadd". It schedules the new types just like "fsmul" and "fdmul".
Tested on frv-elf. Also benchmarked, with no change in score.
OK to install?
Richard
* config/frv/frv.md (define_attr type): Add fscmp, fdcmp, fsmadd and
fdmadd. Remove fmas and m7.
(define_automota fr500_integer, fr500_media): New.
(define_cpu_unit l0): Rename to fr500_load0 and move to fr500_integer.
(define_cpu_unit l1): Likewise fr500_load1.
(define_cpu_unit s0): Likewise fr500_store0.
(define_cpu_unit add0,add1,mul0,mul1): Remove.
(define_cpu_unit m1_0,m1_1,m7): Remove.
(define_cpu_unit m[234]_0,m[234]_1,m5,m6): Add fr500_ prefix.
Move to fr500_media.
(define_insn_reservation b1/b3): Rename to fr500_branch.
(define_insn_reservation b4): Rename to fr500_call.
(define_insn_reservation fr500_farith, fr500_fcmp, fr500_fdiv,
fr500_fsqrt): New, replacing...
(define_insn_reservation f1, f2, f3, f4_div, f4_root): ... these.
(define_insn_reservation i6, b2, b5, b6, f5, f6, f7, m7): Remove.
(define_insn_reservation i2_gload, i2_fload): Combine into fr500_i2.
(define_insn_reservation i3_gstore, i3_fstore): Likewise fr500_i3.
(define_insn_reservation i4_move_fg, i4_move_gf): Likewise fr500_i4.
(define_insn_reservation trap, control): Likewise fr500_control.
(define_insn_reservation m1-m7): Add fr500_ prefix.
(*muladdsf4, *mulsubsf4): Change type to fsmadd.
(*muladddf4, *mulsubdf4): Likewise fdmadd.
(*cmpsf_cc_fp): Likewise fscmp.
(*cmpdf_cc_fp): Likewise fdcmp.
Index: config/frv/frv.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/frv/frv.md,v
retrieving revision 1.4
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.4 frv.md
--- config/frv/frv.md 27 Sep 2003 04:48:17 -0000 1.4
+++ config/frv/frv.md 2 Oct 2003 12:47:42 -0000
@@ -364,7 +364,7 @@ (define_attr "far_jump" "yes,no" (const_
;; mset no n/a m1:1
(define_attr "type"
- "int,sethi,setlo,mul,div,gload,gstore,fload,fstore,movfg,movgf,branch,jump,jumpl,call,spr,trap,fsconv,fsadd,fsmul,fmas,fsdiv,sqrt_single,fdconv,fdadd,fdmul,fddiv,sqrt_double,mlogic,maveh,msath,maddh,mqaddh,mpackh,munpackh,mdpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx,mcut,mclracc,mclracca,mdunpackh,mbhconve,mrdacc,mwtacc,maddacc,mdaddacc,mabsh,mdrot,mcpl,mdcut,mqsath,mset,m7,ccr,multi,unknown"
+ "int,sethi,setlo,mul,div,gload,gstore,fload,fstore,movfg,movgf,branch,jump,jumpl,call,spr,trap,fsconv,fsadd,fscmp,fsmul,fsmadd,fsdiv,sqrt_single,fdconv,fdadd,fdcmp,fdmul,fdmadd,fddiv,sqrt_double,mlogic,maveh,msath,maddh,mqaddh,mpackh,munpackh,mdpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx,mcut,mclracc,mclracca,mdunpackh,mbhconve,mrdacc,mwtacc,maddacc,mdaddacc,mabsh,mdrot,mcpl,mdcut,mqsath,mset,ccr,multi,unknown"
(const_string "unknown"))
@@ -592,224 +592,189 @@ (define_reservation "b1" "sl1_b1|sl2_b1|
;; It is not possibly to issue load & store in one VLIW insn.
(define_cpu_unit "idiv1" "idiv")
(define_cpu_unit "idiv2" "idiv")
-(define_cpu_unit "l0" "nodiv")
-(define_cpu_unit "l1" "nodiv")
-(define_cpu_unit "s0" "nodiv")
-
-(exclusion_set "l1,l0" "s0")
-
-;; We set the default_latency of sethi to be 0 to allow sethi and setlo to be
-;; combined in the same VLIW instruction as allowed by the architecture. This
-;; assumes the only use of sethi is always followed by a setlo of the same
-;; register.
-(define_insn_reservation "i1_sethi" 0
+
+;; Synthetic units used to describe issue restrictions.
+(define_automaton "fr500_integer")
+(define_cpu_unit "fr500_load0,fr500_load1,fr500_store0" "fr500_integer")
+(exclusion_set "fr500_load0,fr500_load1" "fr500_store0")
+
+;; We set the default_latency of sethi to be 0 to allow sethi and setlo
+;; to be combined in the same VLIW instruction. This assumes the only
+;; use of sethi is always followed by a setlo of the same register.
+(define_insn_reservation "fr500_i1_sethi" 0
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "sethi"))
"i0|i1")
-(define_insn_reservation "i1_setlo" 1
+(define_insn_reservation "fr500_i1_setlo" 1
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "setlo"))
"i0|i1")
-(define_insn_reservation "i1_int" 1
+(define_insn_reservation "fr500_i1_int" 1
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "int"))
"i0|i1")
-(define_insn_reservation "i1_mul" 3
+(define_insn_reservation "fr500_i1_mul" 3
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "mul"))
"i0|i1")
-(define_insn_reservation "i1_div" 19
+(define_insn_reservation "fr500_i1_div" 19
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "div"))
"(i0|i1),(idiv1*18|idiv2*18)")
-(define_insn_reservation "i2_gload" 4
- (and (eq_attr "cpu" "generic,fr500,tomcat")
- (eq_attr "type" "gload"))
- "(i0|i1)+(l0|l1)")
-
-(define_insn_reservation "i2_fload" 4
- (and (eq_attr "cpu" "generic,fr500,tomcat")
- (eq_attr "type" "fload"))
- "(i0|i1)+(l0|l1)")
-
-(define_insn_reservation "i3_gstore" 0
+(define_insn_reservation "fr500_i2" 4
(and (eq_attr "cpu" "generic,fr500,tomcat")
- (eq_attr "type" "gstore"))
- "i0+s0")
-
-(define_insn_reservation "i3_fstore" 0
- (and (eq_attr "cpu" "generic,fr500,tomcat")
- (eq_attr "type" "fstore"))
- "i0+s0")
+ (eq_attr "type" "gload,fload"))
+ "(i0|i1) + (fr500_load0|fr500_load1)")
-(define_insn_reservation "i4_move_gf" 3
+(define_insn_reservation "fr500_i3" 0
(and (eq_attr "cpu" "generic,fr500,tomcat")
- (eq_attr "type" "movgf"))
- "i0")
+ (eq_attr "type" "gstore,fstore"))
+ "i0 + fr500_store0")
-(define_insn_reservation "i4_move_fg" 3
+(define_insn_reservation "fr500_i4" 3
(and (eq_attr "cpu" "generic,fr500,tomcat")
- (eq_attr "type" "movfg"))
+ (eq_attr "type" "movgf,movfg"))
"i0")
-(define_insn_reservation "i5" 0
+(define_insn_reservation "fr500_i5" 0
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "jumpl"))
"i0")
-;; Clear/commit is not generated now:
-(define_insn_reservation "i6" 0 (const_int 0) "i0|i1")
-
;;
;; Branch-instructions
;;
-(define_insn_reservation "b1/b3" 0
+(define_insn_reservation "fr500_branch" 0
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "jump,branch,ccr"))
"b0|b1")
-;; The following insn is not generated now.
-
-(define_insn_reservation "b2" 0 (const_int 0) "b0")
-
-(define_insn_reservation "b4" 0
+(define_insn_reservation "fr500_call" 0
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "call"))
"b0")
-;; The following insns are not generated now.
-(define_insn_reservation "b5" 0 (const_int 0) "b0|b1")
-(define_insn_reservation "b6" 0 (const_int 0) "b0|b1")
-
-;; Control insns
-(define_insn_reservation "trap" 0
+;; Control insns.
+(define_insn_reservation "fr500_control" 0
(and (eq_attr "cpu" "generic,fr500,tomcat")
- (eq_attr "type" "trap"))
+ (eq_attr "type" "trap,spr"))
"c")
-(define_insn_reservation "control" 0
- (and (eq_attr "cpu" "generic,fr500,tomcat")
- (eq_attr "type" "spr"))
- "c")
+;; Floating point insns. The default latencies are for non-media
+;; instructions; media instructions incur an extra cycle.
-;; Floating point insns
-(define_cpu_unit "add0" "nodiv")
-(define_cpu_unit "add1" "nodiv")
-(define_cpu_unit "mul0" "nodiv")
-(define_cpu_unit "mul1" "nodiv")
(define_cpu_unit "div1" "div")
(define_cpu_unit "div2" "div")
(define_cpu_unit "root" "div")
-(define_bypass 4 "f1" "m1,m2,m3,m4,m5,m6,m7")
-(define_insn_reservation "f1" 3
+(define_bypass 4 "fr500_farith" "fr500_m1,fr500_m2,fr500_m3,
+ fr500_m4,fr500_m5,fr500_m6")
+(define_insn_reservation "fr500_farith" 3
(and (eq_attr "cpu" "generic,fr500,tomcat")
- (eq_attr "type" "fsconv,fdconv"))
+ (eq_attr "type" "fsconv,fsadd,fsmul,fsmadd,fdconv,fdadd,fdmul,fdmadd"))
"(f0|f1)")
-(define_bypass 4 "f2" "m1,m2,m3,m4,m5,m6,m7")
-(define_insn_reservation "f2" 3
- (and (eq_attr "cpu" "generic,fr500,tomcat")
- (eq_attr "type" "fsadd,fdadd"))
- "(f0|f1)+(add0|add1)")
-
-(define_bypass 4 "f3" "m1,m2,m3,m4,m5,m6,m7")
-(define_insn_reservation "f3" 3
+(define_insn_reservation "fr500_fcmp" 4
(and (eq_attr "cpu" "generic,fr500,tomcat")
- (eq_attr "type" "fsmul,fdmul"))
- "(f0|f1)+(mul0|mul1)")
+ (eq_attr "type" "fscmp,fdcmp"))
+ "(f0|f1)")
-(define_bypass 11 "f4_div" "m1,m2,m3,m4,m5,m6,m7")
-(define_insn_reservation "f4_div" 10
+(define_bypass 11 "fr500_fdiv" "fr500_m1,fr500_m2,fr500_m3,
+ fr500_m4,fr500_m5,fr500_m6")
+(define_insn_reservation "fr500_fdiv" 10
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "fsdiv,fddiv"))
- "(f0|f1),(div1*9|div2*9)")
+ "(f0|f1),(div1*9 | div2*9)")
-(define_bypass 16 "f4_root" "m1,m2,m3,m4,m5,m6,m7")
-(define_insn_reservation "f4_root" 15
+(define_bypass 16 "fr500_froot" "fr500_m1,fr500_m2,fr500_m3,
+ fr500_m4,fr500_m5,fr500_m6")
+(define_insn_reservation "fr500_froot" 15
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "sqrt_single,sqrt_double"))
- "(f0|f1)+root*15")
+ "(f0|f1) + root*15")
-(define_bypass 4 "f5" "m1,m2,m3,m4,m5,m6,m7")
-(define_insn_reservation "f5" 3
- (and (eq_attr "cpu" "generic,fr500,tomcat")
- (eq_attr "type" "fmas"))
- "(f0|f1)+(add0|add1)+(mul0|mul1)")
-
-;; The following insns are not generated by gcc now:
-(define_insn_reservation "f6" 0 (const_int 0) "(f0|f1)+add0+add1")
-(define_insn_reservation "f7" 0 (const_int 0) "(f0|f1)+mul0+mul1")
-
-;; Media insns. Now they are all not generated now.
-(define_cpu_unit "m1_0" "nodiv")
-(define_cpu_unit "m1_1" "nodiv")
-(define_cpu_unit "m2_0" "nodiv")
-(define_cpu_unit "m2_1" "nodiv")
-(define_cpu_unit "m3_0" "nodiv")
-(define_cpu_unit "m3_1" "nodiv")
-(define_cpu_unit "m4_0" "nodiv")
-(define_cpu_unit "m4_1" "nodiv")
-(define_cpu_unit "m5" "nodiv")
-(define_cpu_unit "m6" "nodiv")
-(define_cpu_unit "m7" "nodiv")
-
-(exclusion_set "m5,m6,m7" "m2_0,m2_1,m3_0,m3_1")
-(exclusion_set "m5" "m6,m7")
-(exclusion_set "m6" "m4_0,m4_1,m7")
-(exclusion_set "m7" "m1_0,m1_1,add0,add1,mul0,mul1")
-
-(define_bypass 2 "m1" "m1,m2,m3,m4,m5,m6,m7")
-(define_bypass 4 "m1" "f1,f2,f3,f4_div,f4_root,f5,f6,f7")
-(define_insn_reservation "m1" 3
+;; Media insns. Conflict table is as follows:
+;;
+;; M1 M2 M3 M4 M5 M6
+;; M1 - - - - - -
+;; M2 - - - - X X
+;; M3 - - - - X X
+;; M4 - - - - - X
+;; M5 - X X - X X
+;; M6 - X X X X X
+;;
+;; where X indicates an invalid combination.
+;;
+;; Target registers are as follows:
+;;
+;; M1 : FPRs
+;; M2 : FPRs
+;; M3 : ACCs
+;; M4 : ACCs
+;; M5 : FPRs
+;; M6 : ACCs
+;;
+;; The default FPR latencies are for integer instructions.
+;; Floating-point instructions need one cycle more and media
+;; instructions need one cycle less.
+(define_automaton "fr500_media")
+(define_cpu_unit "fr500_m2_0,fr500_m2_1" "fr500_media")
+(define_cpu_unit "fr500_m3_0,fr500_m3_1" "fr500_media")
+(define_cpu_unit "fr500_m4_0,fr500_m4_1" "fr500_media")
+(define_cpu_unit "fr500_m5" "fr500_media")
+(define_cpu_unit "fr500_m6" "fr500_media")
+
+(exclusion_set "fr500_m5,fr500_m6" "fr500_m2_0,fr500_m2_1,
+ fr500_m3_0,fr500_m3_1")
+(exclusion_set "fr500_m5" "fr500_m6")
+(exclusion_set "fr500_m6" "fr500_m4_0,fr500_m4_1")
+
+(define_bypass 2 "fr500_m1" "fr500_m1,fr500_m2,fr500_m3,
+ fr500_m4,fr500_m5,fr500_m6")
+(define_bypass 4 "fr500_m1" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
+(define_insn_reservation "fr500_m1" 3
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "mlogic,maveh,msath,maddh,mqaddh"))
- "(m0|m1)+(m1_0|m1_1)")
+ "(m0|m1)")
-(define_bypass 2 "m2" "m1,m2,m3,m4,m5,m6,m7")
-(define_bypass 4 "m2" "f1,f2,f3,f4_div,f4_root,f5,f6,f7")
-(define_insn_reservation "m2" 3
+(define_bypass 2 "fr500_m2" "fr500_m1,fr500_m2,fr500_m3,
+ fr500_m4,fr500_m5,fr500_m6")
+(define_bypass 4 "fr500_m2" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
+(define_insn_reservation "fr500_m2" 3
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "mrdacc,mpackh,munpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mcut,mdunpackh,mbhconve"))
- "(m0|m1)+(m2_0|m2_1)")
+ "(m0|m1) + (fr500_m2_0|fr500_m2_1)")
-(define_bypass 1 "m3" "m4")
-(define_insn_reservation "m3" 2
+(define_bypass 1 "fr500_m3" "fr500_m4")
+(define_insn_reservation "fr500_m3" 2
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "mclracc,mwtacc"))
- "(m0|m1)+(m3_0|m3_1)")
+ "(m0|m1) + (fr500_m3_0|fr500_m3_1)")
-(define_bypass 1 "m4" "m4")
-(define_insn_reservation "m4" 2
+(define_bypass 1 "fr500_m4" "fr500_m4")
+(define_insn_reservation "fr500_m4" 2
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx"))
- "(m0|m1)+(m4_0|m4_1)")
+ "(m0|m1) + (fr500_m4_0|fr500_m4_1)")
-(define_bypass 2 "m5" "m1,m2,m3,m4,m5,m6,m7")
-(define_bypass 4 "m5" "f1,f2,f3,f4_div,f4_root,f5,f6,f7")
-(define_insn_reservation "m5" 3
+(define_bypass 2 "fr500_m5" "fr500_m1,fr500_m2,fr500_m3,
+ fr500_m4,fr500_m5,fr500_m6")
+(define_bypass 4 "fr500_m5" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
+(define_insn_reservation "fr500_m5" 3
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "mdpackh"))
- "(m0|m1)+m5")
+ "(m0|m1) + fr500_m5")
-(define_bypass 1 "m6" "m4")
-(define_insn_reservation "m6" 2
+(define_bypass 1 "fr500_m6" "fr500_m4")
+(define_insn_reservation "fr500_m6" 2
(and (eq_attr "cpu" "generic,fr500,tomcat")
(eq_attr "type" "mclracca"))
- "(m0|m1)+m6")
-
-(define_bypass 2 "m7" "m1,m2,m3,m4,m5,m6,m7")
-(define_bypass 4 "m7" "f1,f2,f3,f4_div,f4_root,f5,f6,f7")
-
-(define_insn_reservation "m7" 3
- (and (eq_attr "cpu" "generic,fr500,tomcat")
- (eq_attr "type" "m7"))
- "(m0|m1)+m7")
+ "(m0|m1) + fr500_m6")
;; Unknown & multi insns starts on new cycle and the next insn starts
;; on new cycle. To describe this we consider as a control insn.
@@ -2931,7 +2896,7 @@ (define_insn "*muladdsf4"
"TARGET_HARD_FLOAT && TARGET_MULADD"
"fmadds %1,%2,%0"
[(set_attr "length" "4")
- (set_attr "type" "fmas")])
+ (set_attr "type" "fsmadd")])
(define_insn "*mulsubsf4"
[(set (match_operand:SF 0 "fpr_operand" "=f")
@@ -2941,7 +2906,7 @@ (define_insn "*mulsubsf4"
"TARGET_HARD_FLOAT && TARGET_MULADD"
"fmsubs %1,%2,%0"
[(set_attr "length" "4")
- (set_attr "type" "fmas")])
+ (set_attr "type" "fsmadd")])
;; Division
(define_insn "divsf3"
@@ -3026,7 +2991,7 @@ (define_insn "*muladddf4"
"TARGET_HARD_FLOAT && TARGET_DOUBLE && TARGET_MULADD"
"fmaddd %1,%2,%0"
[(set_attr "length" "4")
- (set_attr "type" "fmas")])
+ (set_attr "type" "fdmadd")])
(define_insn "*mulsubdf4"
[(set (match_operand:DF 0 "fpr_operand" "=f")
@@ -3036,7 +3001,7 @@ (define_insn "*mulsubdf4"
"TARGET_HARD_FLOAT && TARGET_DOUBLE && TARGET_MULADD"
"fmsubd %1,%2,%0"
[(set_attr "length" "4")
- (set_attr "type" "fmas")])
+ (set_attr "type" "fdmadd")])
;; Division
(define_insn "divdf3"
@@ -3485,7 +3450,7 @@ (define_insn "*cmpsf_cc_fp"
"TARGET_HARD_FLOAT"
"fcmps %1,%2,%0"
[(set_attr "length" "4")
- (set_attr "type" "fsadd")])
+ (set_attr "type" "fscmp")])
(define_insn "*cmpdf_cc_fp"
[(set (match_operand:CC_FP 0 "fcc_operand" "=u")
@@ -3494,7 +3459,7 @@ (define_insn "*cmpdf_cc_fp"
"TARGET_HARD_FLOAT && TARGET_DOUBLE"
"fcmpd %1,%2,%0"
[(set_attr "length" "4")
- (set_attr "type" "fdadd")])
+ (set_attr "type" "fdcmp")])
;; ::::::::::::::::::::