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New insns for the s390 backend (3)
- From: Andreas Krebbel <Andreas dot Krebbel at gmx dot de>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 26 Aug 2003 14:31:50 +0200
- Subject: New insns for the s390 backend (3)
Hello,
because the s390 provides two addressing modes (64 and 31 Bit - oh yes 31) it
is often necessary to convert/expand 31 Bit addresses to 64 bit. This is
usually achieved through an ANDwith 7fffffff. Unfortunately this constant is
too big to be used as an immediate value and therefore ends up in the literal
pool. This can be avoided using the llgt and llgtr instructions provided
exactly for that purpose.
Because an AND instruction would additionally set the condition code register
splitters are needed to get rid of the (clobber (reg:CC 33)) rtx.
Bootstrapped/regtested on s390x-ibm-linux.
Ok?
Bye,
Andreas
2003-08-21 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.md ("*llgt_sisi", "*llgt_sisi_split", "*llgt_didi",
"*llgt_didi_split", "*llgt_sidi", "*llgt_sidi_split"): New insns.
Index: gcc/config/s390/s390.md
===================================================================
RCS file: /cvsroot/gcc/gcc/gcc/config/s390/s390.md,v
retrieving revision 1.67
diff -p -c -r1.67 s390.md
*** gcc/config/s390/s390.md 7 Aug 2003 11:05:54 -0000 1.67
--- gcc/config/s390/s390.md 21 Aug 2003 09:18:04 -0000
***************
*** 2426,2431 ****
--- 2426,2502 ----
[(set_attr "op_type" "RXY")])
;
+ ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
+ ;
+
+ (define_insn "*llgt_sisi"
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
+ (const_int 2147483647)))]
+ "TARGET_64BIT"
+ "@
+ llgtr\t%0,%1
+ llgt\t%0,%1"
+ [(set_attr "op_type" "RRE,RXE")])
+
+ (define_insn_and_split "*llgt_sisi_split"
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
+ (const_int 2147483647)))
+ (clobber (reg:CC 33))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (and:SI (match_dup 1)
+ (const_int 2147483647)))]
+ "")
+
+ (define_insn "*llgt_didi"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
+ (const_int 2147483647)))]
+ "TARGET_64BIT"
+ "@
+ llgtr\t%0,%1
+ llgt\t%0,%N1"
+ [(set_attr "op_type" "RRE,RXE")])
+
+ (define_insn_and_split "*llgt_didi_split"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
+ (const_int 2147483647)))
+ (clobber (reg:CC 33))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (and:DI (match_dup 1)
+ (const_int 2147483647)))]
+ "")
+
+ (define_insn "*llgt_sidi"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
+ (const_int 2147483647)))]
+ "TARGET_64BIT"
+ "llgt\t%0,%1"
+ [(set_attr "op_type" "RXE")])
+
+ (define_insn_and_split "*llgt_sidi_split"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
+ (const_int 2147483647)))
+ (clobber (reg:CC 33))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (and:DI (subreg:DI (match_dup 1) 0)
+ (const_int 2147483647)))]
+ "")
+
+ ;
; zero_extendqidi2 instruction pattern(s)
;