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New insns for the s390 backend (2)
- From: Andreas Krebbel <krebbel1 at de dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 26 Aug 2003 13:56:56 +0200
- Subject: New insns for the s390 backend (2)
- Organization: IBM Entwicklung GmbH
Hello,
I've added four new insns to the s390.md file in order to exploit the multiply
and add/sub instructions available on s390 plattform.
Due to the fact that between the two operations no rounding takes place the
result maybe different compared to the same calculation performed with
separated muliply and add/sub instructions. That's why the patterns match
only if unsafe math optimization are allowed (e.g. if the --fast-math
optimization flag is present).
Bootstrapped/regtested on s390x-ibm-linux.
Ok?
Bye,
Andreas
2003-08-21 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.md ("*fmadddf", "*fmsubdf",
"*fmaddsf", "*fmsubsf"): New insns.
Index: gcc/config/s390/s390.md
===================================================================
RCS file: /cvsroot/gcc/gcc/gcc/config/s390/s390.md,v
retrieving revision 1.67
diff -p -c -r1.67 s390.md
*** gcc/config/s390/s390.md 7 Aug 2003 11:05:54 -0000 1.67
--- gcc/config/s390/s390.md 21 Aug 2003 09:15:37 -0000
***************
*** 4033,4038 ****
--- 4033,4062 ----
[(set_attr "op_type" "RR,RX")
(set_attr "type" "fmuld")])
+ (define_insn "*fmadddf"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f")
+ (match_operand:DF 2 "nonimmediate_operand" "f,R"))
+ (match_operand:DF 3 "register_operand" "0,0")))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+ "@
+ madbr\t%0,%1,%2
+ madb\t%0,%1,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fmuld")])
+
+ (define_insn "*fmsubdf"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f")
+ (match_operand:DF 2 "nonimmediate_operand" "f,R"))
+ (match_operand:DF 3 "register_operand" "0,0")))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+ "@
+ msdbr\t%0,%1,%2
+ msdb\t%0,%1,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fmuld")])
+
;
; mulsf3 instruction pattern(s).
;
***************
*** 4070,4075 ****
--- 4094,4122 ----
[(set_attr "op_type" "RR,RX")
(set_attr "type" "fmuls")])
+ (define_insn "*fmaddsf"
+ [(set (match_operand:SF 0 "register_operand" "=f,f")
+ (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f")
+ (match_operand:SF 2 "nonimmediate_operand" "f,R"))
+ (match_operand:SF 3 "register_operand" "0,0")))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+ "@
+ maebr %0,%1,%2
+ maeb %0,%1,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fmuls")])
+
+ (define_insn "*fmsubsf"
+ [(set (match_operand:SF 0 "register_operand" "=f,f")
+ (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f")
+ (match_operand:SF 2 "nonimmediate_operand" "f,R"))
+ (match_operand:SF 3 "register_operand" "0,0")))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+ "@
+ msebr\t%0,%1,%2
+ mseb\t%0,%1,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fmuls")])
;;
;;- Divide and modulo instructions.