Re: [patch] h8300: Fix target/11805

[Kazu Hirata <kazu at cs dot umass dot edu>]

Hi Zack,

> This is a real problem.  I have been idly thinking about a model in
> which the initial RTL claims that there is no condition code; instead
> there are compare-and-branch insns that (if they were output) would
> produce a pair of machine instructions.  So you'd have RTL like this:
> 
> (set (reg:SI 0) (minus:SI (reg:SI 0) (reg:SI 1)))
> 
> (set (pc)
>      (if_then_else (eq:SI (reg:SI 0) (const_int 0))
>                    (label_ref ".L1")
>                    (pc)))
> 
> =>      subl    r0, r1
>         testl   r0
>         beq     .L1

How would you represent a sequence where the result of subtraction is
not needed?  Sometimes you don't want r0 to be destroyed like

  cmpl r0, r1
  beq  .L1

That is,

  if (r0 == r1) goto L1;

Kazu Hirata