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This patch is an attempt to clean up the expanders and asm templates
in mips.md:
- Turn double-backslash sequences like \\t into single-backslash sequenes
- Turn \t\n into \;
- Move to brace syntax instead of:
"*
{
....
}"
- Remove oft-used crud like:
if (operands[0]) /* avoid unused code message */
{
...
}
- Remove fake const0_rtx operands such as:
"*
{
operands[3] = const0_rtx;
return \"subu\\t%L0,%z3,%L1\;...\";
}"
and use %. instead. In many cases, the output template could
then be a constant string.
- Change formatting here and there to make things more consistent.
Although I did the changes by hand, the following sed script
gets close:
/^ "\*$/d
/^ "$/d
s/^}"/}/
s/\\\\/\\/g
s/\\"/"/g
s/\\n\\t/\\;/g
I've attached a -w diff between the output of the script and the version
I'd like to commit. I've also attached the full patch for the record
(although I'm sure no-one would actually want to read it ;).
Tested on the same targets as before. I also checked that the
complicated ffs* and 64-bit shift patterns generated the same
asm code before and after the patch. OK to install?
Richard
* config/mips/mips.md: Quote C code in braces. Remove use of
fake const0_rtx operands. Remove double backslashes. Use \;.
Remove workarounds for bogus warnings.
--- auto.md Sat Aug 16 18:08:29 2003
+++ config/mips.5/mips.md Thu Aug 14 16:12:23 2003
@@ -765,6 +765,7 @@
{
if (REGNO (operands[0]) == REGNO (operands[1]))
return "addu\t%0,%2";
+ else
return "addu\t%0,%1,%2";
}
[(set_attr "type" "arith")
@@ -1081,6 +1082,7 @@
{
if (REGNO (operands[0]) == REGNO (operands[1]))
return "daddu\t%0,%2";
+ else
return "daddu\t%0,%1,%2";
}
[(set_attr "type" "arith")
@@ -1181,6 +1183,7 @@
{
if (REGNO (operands[0]) == REGNO (operands[1]))
return "addu\t%0,%2";
+ else
return "addu\t%0,%1,%2";
}
[(set_attr "type" "arith")
@@ -1729,11 +1732,10 @@
(clobber (match_scratch:SI 5 "=X,1,l"))
(clobber (match_scratch:SI 6 "=X,X,&d"))]
"ISA_HAS_MADD_MSUB"
-{
- if (which_alternative != 0)
- return "#";
- return "msub\t%2,%3";
-}
+ "@
+ msub\t%2,%3
+ #
+ #"
[(set_attr "type" "imadd,multi,multi")
(set_attr "mode" "SI")
(set_attr "length" "4,8,8")])
@@ -1815,7 +1817,6 @@
(mult:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" "")))]
"TARGET_64BIT"
-
{
if (GENERATE_MULT3_DI || TARGET_MIPS4000)
emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
@@ -2560,26 +2561,24 @@
(clobber (match_scratch:SI 3 "=&d"))]
"!TARGET_MIPS16"
{
- operands[4] = const0_rtx;
-
if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
return "%(\
-move\t%0,%z4\n\
-\tbeq\t%1,%z4,2f\n\
-%~1:\tand\t%2,%1,0x0001\n\
-\taddu\t%0,%0,1\n\
-\tbeq\t%2,%z4,1b\n\
-\tsrl\t%1,%1,1\n\
+move\t%0,%.\;\
+beq\t%1,%.,2f\n\
+%~1:\tand\t%2,%1,0x0001\;\
+addu\t%0,%0,1\;\
+beq\t%2,%.,1b\;\
+srl\t%1,%1,1\n\
%~2:%)";
return "%(\
-move\t%0,%z4\n\
-\tmove\t%3,%1\n\
-\tbeq\t%3,%z4,2f\n\
-%~1:\tand\t%2,%3,0x0001\n\
-\taddu\t%0,%0,1\n\
-\tbeq\t%2,%z4,1b\n\
-\tsrl\t%3,%3,1\n\
+move\t%0,%.\;\
+move\t%3,%1\;\
+beq\t%3,%.,2f\n\
+%~1:\tand\t%2,%3,0x0001\;\
+addu\t%0,%0,1\;\
+beq\t%2,%.,1b\;\
+srl\t%3,%3,1\n\
%~2:%)";
}
[(set_attr "type" "multi")
@@ -2593,26 +2592,24 @@
(clobber (match_scratch:DI 3 "=&d"))]
"TARGET_64BIT && !TARGET_MIPS16"
{
- operands[4] = const0_rtx;
-
if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
return "%(\
-move\t%0,%z4\n\
-\tbeq\t%1,%z4,2f\n\
-%~1:\tand\t%2,%1,0x0001\n\
-\tdaddu\t%0,%0,1\n\
-\tbeq\t%2,%z4,1b\n\
-\tdsrl\t%1,%1,1\n\
+move\t%0,%.\;\
+beq\t%1,%.,2f\n\
+%~1:\tand\t%2,%1,0x0001\;\
+daddu\t%0,%0,1\;\
+beq\t%2,%.,1b\;\
+dsrl\t%1,%1,1\n\
%~2:%)";
return "%(\
-move\t%0,%z4\n\
-\tmove\t%3,%1\n\
-\tbeq\t%3,%z4,2f\n\
-%~1:\tand\t%2,%3,0x0001\n\
-\tdaddu\t%0,%0,1\n\
-\tbeq\t%2,%z4,1b\n\
-\tdsrl\t%3,%3,1\n\
+move\t%0,%.\;\
+move\t%3,%1\;\
+beq\t%3,%.,2f\n\
+%~1:\tand\t%2,%3,0x0001\;\
+daddu\t%0,%0,1\;\
+beq\t%2,%.,1b\;\
+dsrl\t%3,%3,1\n\
%~2:%)";
}
[(set_attr "type" "multi")
@@ -2657,8 +2654,8 @@
{
if (TARGET_MIPS16)
return "neg\t%0,%1";
- operands[2] = const0_rtx;
- return "subu\t%0,%z2,%1";
+ else
+ return "subu\t%0,%.,%1";
}
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
@@ -2683,10 +2680,7 @@
(neg:DI (match_operand:DI 1 "register_operand" "d")))
(clobber (match_operand:SI 2 "register_operand" "=d"))]
"! TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-{
- operands[3] = const0_rtx;
- return "subu\t%L0,%z3,%L1\;subu\t%M0,%z3,%M1\;sltu\t%2,%z3,%L0\;subu\t%M0,%M0,%2";
-}
+ "subu\t%L0,%.,%L1\;subu\t%M0,%.,%M1\;sltu\t%2,%.,%L0\;subu\t%M0,%M0,%2"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
(set_attr "length" "16")])
@@ -2695,10 +2689,7 @@
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (match_operand:DI 1 "register_operand" "d")))]
"TARGET_64BIT && !TARGET_MIPS16"
-{
- operands[2] = const0_rtx;
- return "dsubu\t%0,%z2,%1";
-}
+ "dsubu\t%0,%.,%1"
[(set_attr "type" "arith")
(set_attr "mode" "DI")])
@@ -2725,8 +2716,8 @@
{
if (TARGET_MIPS16)
return "not\t%0,%1";
- operands[2] = const0_rtx;
- return "nor\t%0,%z2,%1";
+ else
+ return "nor\t%0,%.,%1";
}
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
@@ -2738,6 +2729,7 @@
{
if (TARGET_MIPS16)
return "not\t%0,%1";
+ else
return "nor\t%0,%.,%1";
}
[(set_attr "type" "darith")
@@ -3349,10 +3341,10 @@
{
if (symbolic_operand (operands[1], SImode))
{
- emit_move_insn (operands[0], convert_memory_address (DImode, operands[1]));
+ emit_move_insn (operands[0],
+ convert_memory_address (DImode, operands[1]));
DONE;
}
-
})
(define_insn "*extendsidi2"
@@ -3407,13 +3399,14 @@
[(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
""
+{
if (ISA_HAS_SEB_SEH)
{
emit_insn (gen_extendhisi2_hw (operands[0],
force_reg (HImode, operands[1])));
DONE;
}
-")
+})
(define_insn "*extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=d")
@@ -3483,13 +3476,14 @@
[(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
""
+{
if (ISA_HAS_SEB_SEH)
{
emit_insn (gen_extendqisi2_hw (operands[0],
force_reg (QImode, operands[1])));
DONE;
}
-")
+})
(define_insn "*extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=d")
@@ -3597,6 +3591,7 @@
{
if (set_nomacro)
return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
+ else
return "trunc.w.d %0,%1,%2";
}
[(set_attr "type" "fcvt")
@@ -3632,6 +3627,7 @@
{
if (set_nomacro)
return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
+ else
return "trunc.w.s %0,%1,%2";
}
[(set_attr "type" "fcvt")
@@ -3758,8 +3754,6 @@
real_2expN (&offset, 63);
- if (reg1) /* turn off complaints about unreached code */
- {
emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
do_pending_stack_adjust ();
@@ -3785,7 +3779,6 @@
fields, and can't be used for REG_NOTES anyway). */
emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
DONE;
- }
})
@@ -3803,8 +3796,6 @@
real_2expN (&offset, 31);
- if (reg1) /* turn off complaints about unreached code */
- {
emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
do_pending_stack_adjust ();
@@ -3830,7 +3821,6 @@
fields, and can't be used for REG_NOTES anyway). */
emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
DONE;
- }
})
@@ -3848,8 +3838,6 @@
real_2expN (&offset, 63);
- if (reg1) /* turn off complaints about unreached code */
- {
emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
do_pending_stack_adjust ();
@@ -3875,7 +3863,6 @@
fields, and can't be used for REG_NOTES anyway). */
emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
DONE;
- }
})
;;
@@ -4386,9 +4373,7 @@
&& INTVAL (operands[1]) > - 0x8000"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 0) (neg:SI (match_dup 0)))]
-{
- operands[1] = GEN_INT (- INTVAL (operands[1]));
-})
+ { operands[1] = GEN_INT (- INTVAL (operands[1])); })
;; This insn handles moving CCmode values. It's really just a
;; slightly simplified copy of movsi_internal2, with additional cases
@@ -5066,10 +5051,7 @@
&& INTVAL (operands[2]) <= 16"
[(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 8)))
(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-})
+ { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
(define_expand "ashldi3"
[(parallel [(set (match_operand:DI 0 "register_operand" "")
@@ -5118,26 +5100,22 @@
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_operand:SI 3 "register_operand" "=d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-{
- operands[4] = const0_rtx;
-
- return "sll\t%3,%2,26\n\
-\tbgez\t%3,1f%#\n\
-\tsll\t%M0,%L1,%2\n\
-\t%(b\t3f\n\
-\tmove\t%L0,%z4%)\n\
-\n\
-%~1:\n\
-\t%(beq\t%3,%z4,2f\n\
-\tsll\t%M0,%M1,%2%)\n\
-\n\
-\tsubu\t%3,%z4,%2\n\
-\tsrl\t%3,%L1,%3\n\
-\tor\t%M0,%M0,%3\n\
-%~2:\n\
-\tsll\t%L0,%L1,%2\n\
-%~3:";
-}
+ "sll\t%3,%2,26\;\
+bgez\t%3,1f%#\;\
+sll\t%M0,%L1,%2\;\
+%(b\t3f\;\
+move\t%L0,%.%)\
+\n\n\
+%~1:\;\
+%(beq\t%3,%.,2f\;\
+sll\t%M0,%M1,%2%)\
+\n\;\
+subu\t%3,%.,%2\;\
+srl\t%3,%L1,%3\;\
+or\t%M0,%M0,%3\n\
+%~2:\;\
+sll\t%L0,%L1,%2\n\
+%~3:"
[(set_attr "type" "darith")
(set_attr "mode" "SI")
(set_attr "length" "48")])
@@ -5152,8 +5130,7 @@
&& (INTVAL (operands[2]) & 32) != 0"
{
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- operands[4] = const0_rtx;
- return "sll\t%M0,%L1,%2\;move\t%L0,%z4";
+ return "sll\t%M0,%L1,%2\;move\t%L0,%.";
}
[(set_attr "type" "darith")
(set_attr "mode" "DI")
@@ -5206,10 +5183,9 @@
int amount = INTVAL (operands[2]);
operands[2] = GEN_INT (amount & 31);
- operands[4] = const0_rtx;
- operands[5] = GEN_INT ((-amount) & 31);
+ operands[4] = GEN_INT ((-amount) & 31);
- return "sll\t%M0,%M1,%2\;srl\t%3,%L1,%5\;or\t%M0,%M0,%3\;sll\t%L0,%L1,%2";
+ return "sll\t%M0,%M1,%2\;srl\t%3,%L1,%4\;or\t%M0,%M0,%3\;sll\t%L0,%L1,%2";
}
[(set_attr "type" "darith")
(set_attr "mode" "DI")
@@ -5334,10 +5310,7 @@
&& INTVAL (operands[2]) <= 16"
[(set (match_dup 0) (ashift:DI (match_dup 1) (const_int 8)))
(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-})
+ { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
(define_expand "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
@@ -5414,10 +5387,7 @@
&& INTVAL (operands[2]) <= 16"
[(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 8)))
(set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-})
+ { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
(define_expand "ashrdi3"
[(parallel [(set (match_operand:DI 0 "register_operand" "")
@@ -5462,26 +5432,22 @@
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_operand:SI 3 "register_operand" "=d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-{
- operands[4] = const0_rtx;
-
- return "sll\t%3,%2,26\n\
-\tbgez\t%3,1f%#\n\
-\tsra\t%L0,%M1,%2\n\
-\t%(b\t3f\n\
-\tsra\t%M0,%M1,31%)\n\
-\n\
-%~1:\n\
-\t%(beq\t%3,%z4,2f\n\
-\tsrl\t%L0,%L1,%2%)\n\
-\n\
-\tsubu\t%3,%z4,%2\n\
-\tsll\t%3,%M1,%3\n\
-\tor\t%L0,%L0,%3\n\
-%~2:\n\
-\tsra\t%M0,%M1,%2\n\
-%~3:";
-}
+ "sll\t%3,%2,26\;\
+bgez\t%3,1f%#\;\
+sra\t%L0,%M1,%2\;\
+%(b\t3f\;\
+sra\t%M0,%M1,31%)\
+\n\n\
+%~1:\;\
+%(beq\t%3,%.,2f\;\
+srl\t%L0,%L1,%2%)\
+\n\;\
+subu\t%3,%.,%2\;\
+sll\t%3,%M1,%3\;\
+or\t%L0,%L0,%3\n\
+%~2:\;\
+sra\t%M0,%M1,%2\n\
+%~3:"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
(set_attr "length" "48")])
@@ -5671,10 +5637,7 @@
&& INTVAL (operands[2]) <= 16"
[(set (match_dup 0) (ashiftrt:DI (match_dup 1) (const_int 8)))
(set (match_dup 0) (ashiftrt:DI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-})
+ { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
(define_expand "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
@@ -5751,10 +5714,7 @@
&& INTVAL (operands[2]) <= 16"
[(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 8)))
(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-})
+ { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
;; If we load a byte on the mips16 as a bitfield, the resulting
;; sequence of instructions is too complicated for combine, because it
@@ -5829,26 +5789,22 @@
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_operand:SI 3 "register_operand" "=d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-{
- operands[4] = const0_rtx;
-
- return "sll\t%3,%2,26\n\
-\tbgez\t%3,1f%#\n\
-\tsrl\t%L0,%M1,%2\n\
-\t%(b\t3f\n\
-\tmove\t%M0,%z4%)\n\
-\n\
-%~1:\n\
-\t%(beq\t%3,%z4,2f\n\
-\tsrl\t%L0,%L1,%2%)\n\
-\n\
-\tsubu\t%3,%z4,%2\n\
-\tsll\t%3,%M1,%3\n\
-\tor\t%L0,%L0,%3\n\
-%~2:\n\
-\tsrl\t%M0,%M1,%2\n\
-%~3:";
-}
+ "sll\t%3,%2,26\;\
+bgez\t%3,1f%#\;\
+srl\t%L0,%M1,%2\;\
+%(b\t3f\;\
+move\t%M0,%.%)\
+\n\n\
+%~1:\;\
+%(beq\t%3,%.,2f\;\
+srl\t%L0,%L1,%2%)\
+\n\;\
+subu\t%3,%.,%2\;\
+sll\t%3,%M1,%3\;\
+or\t%L0,%L0,%3\n\
+%~2:\;\
+srl\t%M0,%M1,%2\n\
+%~3:"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
(set_attr "length" "48")])
@@ -5863,8 +5819,7 @@
&& (INTVAL (operands[2]) & 32) != 0"
{
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- operands[4] = const0_rtx;
- return "srl\t%L0,%M1,%2\;move\t%M0,%z4";
+ return "srl\t%L0,%M1,%2\;move\t%M0,%.";
}
[(set_attr "type" "darith")
(set_attr "mode" "DI")
@@ -6082,10 +6037,7 @@
&& INTVAL (operands[2]) <= 16"
[(set (match_dup 0) (lshiftrt:DI (match_dup 1) (const_int 8)))
(set (match_dup 0) (lshiftrt:DI (match_dup 0) (match_dup 2)))]
-"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-})
+ { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
;;
;; ....................
@@ -6116,13 +6068,10 @@
(match_operand:SI 1 "arith_operand" "")))]
""
{
- if (operands[0]) /* avoid unused code message */
- {
branch_cmp[0] = operands[0];
branch_cmp[1] = operands[1];
branch_type = CMP_SI;
DONE;
- }
})
(define_expand "tstsi"
@@ -6130,13 +6079,10 @@
(match_operand:SI 0 "register_operand" ""))]
""
{
- if (operands[0]) /* avoid unused code message */
- {
branch_cmp[0] = operands[0];
branch_cmp[1] = const0_rtx;
branch_type = CMP_SI;
DONE;
- }
})
(define_expand "cmpdi"
@@ -6145,13 +6091,10 @@
(match_operand:DI 1 "arith_operand" "")))]
"TARGET_64BIT"
{
- if (operands[0]) /* avoid unused code message */
- {
branch_cmp[0] = operands[0];
branch_cmp[1] = operands[1];
branch_type = CMP_DI;
DONE;
- }
})
(define_expand "tstdi"
@@ -6159,13 +6102,10 @@
(match_operand:DI 0 "register_operand" ""))]
"TARGET_64BIT"
{
- if (operands[0]) /* avoid unused code message */
- {
branch_cmp[0] = operands[0];
branch_cmp[1] = const0_rtx;
branch_type = CMP_DI;
DONE;
- }
})
(define_expand "cmpdf"
@@ -6174,13 +6114,10 @@
(match_operand:DF 1 "register_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
{
- if (operands[0]) /* avoid unused code message */
- {
branch_cmp[0] = operands[0];
branch_cmp[1] = operands[1];
branch_type = CMP_DF;
DONE;
- }
})
(define_expand "cmpsf"
@@ -6189,13 +6126,10 @@
(match_operand:SF 1 "register_operand" "")))]
"TARGET_HARD_FLOAT"
{
- if (operands[0]) /* avoid unused code message */
- {
branch_cmp[0] = operands[0];
branch_cmp[1] = operands[1];
branch_type = CMP_SF;
DONE;
- }
})
;;
@@ -6477,11 +6411,8 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, UNORDERED);
DONE;
- }
})
(define_expand "bordered"
@@ -6492,11 +6423,8 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, ORDERED);
DONE;
- }
})
(define_expand "bunlt"
@@ -6507,11 +6435,8 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, UNLT);
DONE;
- }
})
(define_expand "bunge"
@@ -6534,11 +6459,8 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, UNEQ);
DONE;
- }
})
(define_expand "bltgt"
@@ -6561,11 +6483,8 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, UNLE);
DONE;
- }
})
(define_expand "bungt"
@@ -6588,11 +6507,8 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, EQ);
DONE;
- }
})
(define_expand "bne"
@@ -6603,11 +6519,8 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, NE);
DONE;
- }
})
(define_expand "bgt"
@@ -6618,11 +6531,8 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, GT);
DONE;
- }
})
(define_expand "bge"
@@ -6633,11 +6543,8 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, GE);
DONE;
- }
})
(define_expand "blt"
@@ -6648,11 +6555,8 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, LT);
DONE;
- }
})
(define_expand "ble"
@@ -6663,11 +6567,8 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, LE);
DONE;
- }
})
(define_expand "bgtu"
@@ -6678,11 +6579,8 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, GTU);
DONE;
- }
})
(define_expand "bgeu"
@@ -6693,14 +6591,10 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, GEU);
DONE;
- }
})
-
(define_expand "bltu"
[(set (pc)
(if_then_else (ltu:CC (cc0)
@@ -6709,11 +6603,8 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, LTU);
DONE;
- }
})
(define_expand "bleu"
@@ -6724,11 +6615,8 @@
(pc)))]
""
{
- if (operands[0]) /* avoid unused code warning */
- {
gen_conditional_branch (operands, LEU);
DONE;
- }
})
;;
@@ -7827,8 +7715,6 @@
{
rtx dest;
- if (operands[0]) /* eliminate unused code warnings */
- {
dest = operands[0];
if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
operands[0] = copy_to_mode_reg (Pmode, dest);
@@ -7839,7 +7725,6 @@
emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
DONE;
- }
})
(define_insn "indirect_jump_internal1"
@@ -7862,8 +7747,6 @@
(use (label_ref (match_operand 1 "" "")))]
""
{
- if (operands[0]) /* eliminate unused code warnings */
- {
if (TARGET_MIPS16)
{
if (GET_MODE (operands[0]) != HImode)
@@ -7887,7 +7770,6 @@
else
emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
DONE;
- }
})
(define_insn "tablejump_internal1"
@@ -7914,8 +7796,6 @@
(label_ref:SI (match_operand 1 "" ""))))]
"TARGET_MIPS16 && !(Pmode == DImode)"
{
- if (operands[0]) /* eliminate unused code warnings. */
- {
rtx t1, t2, t3;
t1 = gen_reg_rtx (SImode);
@@ -7926,7 +7806,6 @@
emit_insn (gen_addsi3 (t3, t1, t2));
emit_jump_insn (gen_tablejump_internal1 (t3, operands[1]));
DONE;
- }
})
(define_expand "tablejump_mips162"
@@ -7935,8 +7814,6 @@
(label_ref:DI (match_operand 1 "" ""))))]
"TARGET_MIPS16 && Pmode == DImode"
{
- if (operands[0]) /* eliminate unused code warnings. */
- {
rtx t1, t2, t3;
t1 = gen_reg_rtx (DImode);
@@ -7947,7 +7824,6 @@
emit_insn (gen_adddi3 (t3, t1, t2));
emit_jump_insn (gen_tablejump_internal2 (t3, operands[1]));
DONE;
- }
})
;; Implement a switch statement when generating embedded PIC code.
@@ -7974,8 +7850,6 @@
(clobber (reg:SI 31))])]
"TARGET_EMBEDDED_PIC"
{
- if (operands[0])
- {
rtx index;
/* If the index is too large, go to the default label. */
@@ -7993,7 +7867,6 @@
gen_reg_rtx (DImode)));
DONE;
- }
})
;; An embedded PIC switch statement looks like this:
@@ -8101,11 +7974,8 @@
[(const_int 1)]
""
{
- if (mips_isa >= 0) /* avoid unused code warnings */
- {
mips_expand_prologue ();
DONE;
- }
})
;; Block any insns from being moved before this point, since the
@@ -8452,7 +8322,7 @@
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))]
"ISA_HAS_PREFETCH && Pmode == SImode"
- "* return mips_emit_prefetch (operands);"
+ { return mips_emit_prefetch (operands); }
[(set_attr "type" "prefetch")])
(define_insn "prefetch_si"
@@ -8460,7 +8330,7 @@
(match_operand:SI 1 "const_int_operand" "n")
(match_operand:SI 2 "const_int_operand" "n"))]
"ISA_HAS_PREFETCH && Pmode == SImode"
- "* return mips_emit_prefetch (operands);"
+ { return mips_emit_prefetch (operands); }
[(set_attr "type" "prefetch")])
(define_insn "prefetch_di_address"
@@ -8469,7 +8339,7 @@
(match_operand:DI 1 "const_int_operand" "n")
(match_operand:DI 2 "const_int_operand" "n"))]
"ISA_HAS_PREFETCH && Pmode == DImode"
- "* return mips_emit_prefetch (operands);"
+ { return mips_emit_prefetch (operands); }
[(set_attr "type" "prefetch")])
(define_insn "prefetch_di"
@@ -8477,7 +8347,7 @@
(match_operand:DI 1 "const_int_operand" "n")
(match_operand:DI 2 "const_int_operand" "n"))]
"ISA_HAS_PREFETCH && Pmode == DImode"
- "* return mips_emit_prefetch (operands);"
+ { return mips_emit_prefetch (operands); }
[(set_attr "type" "prefetch")])
(define_insn "nop"
Attachment:
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Description: BZip2 compressed data
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