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[PATCH] Some simplify_binary_operation improvements.

The following patch cleans up simplify_binary_operation, by replacing
calls to gen_rtx_* with calls to the preferred simplify_gen_unary and
simplify_gen_binary.  These changes allow some complex RTL expressions
to be simplified even further.

The following patch has been tested on i686-pc-linux-gnu with a full
"make bootstrap", all languages except treelang, and regression tested
with a top-level "make -k check" with no new failures.

Ok for mainline?


2003-08-10  Roger Sayle  <roger@eyesopen.com>

	* simplify-rtx.c (simplify_binary_operation): Replace calls to
	gen_rtx_NEG and gen_rtx_NOT with calls to simplify_gen_unary,
	and calls to gen_rtx_PLUS, gen_rtx_MULT, gen_rtx_LSHIFTRT,
	gen_rtx_ASHIFT and gen_rtx_AND with calls to simplify_gen_binary.


Index: simplify-rtx.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/simplify-rtx.c,v
retrieving revision 1.151
diff -c -3 -p -r1.151 simplify-rtx.c
*** simplify-rtx.c	19 Jul 2003 14:47:13 -0000	1.151
--- simplify-rtx.c	10 Aug 2003 19:00:21 -0000
*************** simplify_binary_operation (enum rtx_code
*** 1095,1101 ****
  	  if (INTEGRAL_MODE_P (mode)
  	      && GET_CODE (op0) == NOT
  	      && trueop1 == const1_rtx)
! 	    return gen_rtx_NEG (mode, XEXP (op0, 0));

  	  /* Handle both-operands-constant cases.  We can only add
  	     CONST_INTs to constants since the sum of relocatable symbols
--- 1095,1101 ----
  	  if (INTEGRAL_MODE_P (mode)
  	      && GET_CODE (op0) == NOT
  	      && trueop1 == const1_rtx)
! 	    return simplify_gen_unary (NEG, mode, XEXP (op0, 0), mode);

  	  /* Handle both-operands-constant cases.  We can only add
  	     CONST_INTs to constants since the sum of relocatable symbols
*************** simplify_binary_operation (enum rtx_code
*** 1230,1240 ****
  	     But if the mode has signed zeros, and does not round towards
  	     -infinity, then 0 - 0 is 0, not -0.  */
  	  if (!HONOR_SIGNED_ZEROS (mode) && trueop0 == CONST0_RTX (mode))
! 	    return gen_rtx_NEG (mode, op1);

  	  /* (-1 - a) is ~a.  */
  	  if (trueop0 == constm1_rtx)
! 	    return gen_rtx_NOT (mode, op1);

  	  /* Subtracting 0 has no effect unless the mode has signed zeros
  	     and supports rounding towards -infinity.  In such a case,
--- 1230,1240 ----
  	     But if the mode has signed zeros, and does not round towards
  	     -infinity, then 0 - 0 is 0, not -0.  */
  	  if (!HONOR_SIGNED_ZEROS (mode) && trueop0 == CONST0_RTX (mode))
! 	    return simplify_gen_unary (NEG, mode, op1, mode);

  	  /* (-1 - a) is ~a.  */
  	  if (trueop0 == constm1_rtx)
! 	    return simplify_gen_unary (NOT, mode, op1, mode);

  	  /* Subtracting 0 has no effect unless the mode has signed zeros
  	     and supports rounding towards -infinity.  In such a case,
*************** simplify_binary_operation (enum rtx_code
*** 1344,1354 ****

  	case MULT:
  	  if (trueop1 == constm1_rtx)
! 	    {
! 	      tem = simplify_unary_operation (NEG, mode, op0, mode);
!
! 	      return tem ? tem : gen_rtx_NEG (mode, op0);
! 	    }

  	  /* Maybe simplify x * 0 to 0.  The reduction is not valid if
  	     x is NaN, since x * 0 is then also NaN.  Nor is it valid
--- 1344,1350 ----

  	case MULT:
  	  if (trueop1 == constm1_rtx)
! 	    return simplify_gen_unary (NEG, mode, op0, mode);

  	  /* Maybe simplify x * 0 to 0.  The reduction is not valid if
  	     x is NaN, since x * 0 is then also NaN.  Nor is it valid
*************** simplify_binary_operation (enum rtx_code
*** 1376,1382 ****
  	      && (width <= HOST_BITS_PER_WIDE_INT
  		  || val != HOST_BITS_PER_WIDE_INT - 1)
  	      && ! rtx_equal_function_value_matters)
! 	    return gen_rtx_ASHIFT (mode, op0, GEN_INT (val));

  	  /* x*2 is x+x and x*(-1) is -x */
  	  if (GET_CODE (trueop1) == CONST_DOUBLE
--- 1372,1378 ----
  	      && (width <= HOST_BITS_PER_WIDE_INT
  		  || val != HOST_BITS_PER_WIDE_INT - 1)
  	      && ! rtx_equal_function_value_matters)
! 	    return simplify_gen_binary (ASHIFT, mode, op0, GEN_INT (val));

  	  /* x*2 is x+x and x*(-1) is -x */
  	  if (GET_CODE (trueop1) == CONST_DOUBLE
*************** simplify_binary_operation (enum rtx_code
*** 1387,1396 ****
  	      REAL_VALUE_FROM_CONST_DOUBLE (d, trueop1);

  	      if (REAL_VALUES_EQUAL (d, dconst2))
! 		return gen_rtx_PLUS (mode, op0, copy_rtx (op0));

  	      if (REAL_VALUES_EQUAL (d, dconstm1))
! 		return gen_rtx_NEG (mode, op0);
  	    }
  	  break;

--- 1383,1392 ----
  	      REAL_VALUE_FROM_CONST_DOUBLE (d, trueop1);

  	      if (REAL_VALUES_EQUAL (d, dconst2))
! 		return simplify_gen_binary (PLUS, mode, op0, copy_rtx (op0));

  	      if (REAL_VALUES_EQUAL (d, dconstm1))
! 		return simplify_gen_unary (NEG, mode, op0, mode);
  	    }
  	  break;

*************** simplify_binary_operation (enum rtx_code
*** 1417,1423 ****
  	  if (GET_CODE (trueop1) == CONST_INT
  	      && ((INTVAL (trueop1) & GET_MODE_MASK (mode))
  		  == GET_MODE_MASK (mode)))
! 	    return gen_rtx_NOT (mode, op0);
  	  if (trueop0 == trueop1 && ! side_effects_p (op0)
  	      && GET_MODE_CLASS (mode) != MODE_CC)
  	    return const0_rtx;
--- 1413,1419 ----
  	  if (GET_CODE (trueop1) == CONST_INT
  	      && ((INTVAL (trueop1) & GET_MODE_MASK (mode))
  		  == GET_MODE_MASK (mode)))
! 	    return simplify_gen_unary (NOT, mode, op0, mode);
  	  if (trueop0 == trueop1 && ! side_effects_p (op0)
  	      && GET_MODE_CLASS (mode) != MODE_CC)
  	    return const0_rtx;
*************** simplify_binary_operation (enum rtx_code
*** 1446,1452 ****
  	     below).  */
  	  if (GET_CODE (trueop1) == CONST_INT
  	      && (arg1 = exact_log2 (INTVAL (trueop1))) > 0)
! 	    return gen_rtx_LSHIFTRT (mode, op0, GEN_INT (arg1));

  	  /* ... fall through ...  */

--- 1442,1448 ----
  	     below).  */
  	  if (GET_CODE (trueop1) == CONST_INT
  	      && (arg1 = exact_log2 (INTVAL (trueop1))) > 0)
! 	    return simplify_gen_binary (LSHIFTRT, mode, op0, GEN_INT (arg1));

  	  /* ... fall through ...  */

*************** simplify_binary_operation (enum rtx_code
*** 1487,1494 ****
  	      if (! REAL_VALUES_EQUAL (d, dconst0))
  		{
  		  REAL_ARITHMETIC (d, rtx_to_tree_code (DIV), dconst1, d);
! 		  return gen_rtx_MULT (mode, op0,
! 				       CONST_DOUBLE_FROM_REAL_VALUE (d, mode));
  		}
  	    }
  	  break;
--- 1483,1490 ----
  	      if (! REAL_VALUES_EQUAL (d, dconst0))
  		{
  		  REAL_ARITHMETIC (d, rtx_to_tree_code (DIV), dconst1, d);
! 		  tem = CONST_DOUBLE_FROM_REAL_VALUE (d, mode);
! 		  return simplify_gen_binary (MULT, mode, op0, tem);
  		}
  	    }
  	  break;
*************** simplify_binary_operation (enum rtx_code
*** 1497,1503 ****
  	  /* Handle modulus by power of two (mod with 1 handled below).  */
  	  if (GET_CODE (trueop1) == CONST_INT
  	      && exact_log2 (INTVAL (trueop1)) > 0)
! 	    return gen_rtx_AND (mode, op0, GEN_INT (INTVAL (op1) - 1));

  	  /* ... fall through ...  */

--- 1493,1500 ----
  	  /* Handle modulus by power of two (mod with 1 handled below).  */
  	  if (GET_CODE (trueop1) == CONST_INT
  	      && exact_log2 (INTVAL (trueop1)) > 0)
! 	    return simplify_gen_binary (AND, mode, op0,
! 					GEN_INT (INTVAL (op1) - 1));

  	  /* ... fall through ...  */


Roger
--
Roger Sayle,                         E-mail: roger@eyesopen.com
OpenEye Scientific Software,         WWW: http://www.eyesopen.com/
Suite 1107, 3600 Cerrillos Road,     Tel: (+1) 505-473-7385
Santa Fe, New Mexico, 87507.         Fax: (+1) 505-473-0833
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