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New insns for the s390 backend
- From: Andreas Krebbel <krebbel1 at de dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 1 Aug 2003 15:43:36 +0200
- Subject: New insns for the s390 backend
- Organization: IBM Entwicklung GmbH
Hello,
the following patch introduces several new insn patterns into the s390
backend.
The first group ("*addsf3_cc", "*addsf3_cconly" ...) is intended to exploit
the condition codes set by add and sub instructions on floating point
numbers. So far redundant comparison instructions were created in cases like:
if (a + b == 0) ...
Now the newly introduced insns match with patterns created by the combiner
causing the additional comparison instructions to be omitted. Therefore the
s390.c had to be modified to avoid usage of CCL modes with add and sub
operations on floats.
The patterns "*negabssi2", "*negabsdi2", "*negabsdf2", "*negabssf2" exploit
the lnr, lngr, lnebr and lndbr (load negative) instructions available on s390
platform in order to implement expressions like -abs(a) and -fabs(b).
Bootstrapped/regtested on s390x-ibm-linux.
Ok?
Bye,
Andreas
2003-07-31 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.c (s390_select_ccmode): Do not attempt to use CCL,
CCL1, or CCL2 modes with floating point operations.
* config/s390/s390.md ("*addsf3_cc", "*addsf3_cconly", "*adddf3_cc",
"*adddf3_cconly", "*subsf3_cc", "*subsf3_cconly", "*subdf3_cc",
"*subdf3_cconly"): New insns.
("*negabssi2", "*negabsdi2", "*negabsdf2", "*negabssf2"): Likewise.
Index: gcc/config/s390/s390.c
===================================================================
RCS file: /cvsroot/gcc/gcc/gcc/config/s390/s390.c,v
retrieving revision 1.105
diff -p -c -r1.105 s390.c
*** gcc/config/s390/s390.c 22 Jul 2003 17:38:13 -0000 1.105
--- gcc/config/s390/s390.c 31 Jul 2003 14:13:19 -0000
*************** s390_select_ccmode (code, op0, op1)
*** 377,384 ****
if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
&& CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K'))
return CCAPmode;
! if (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
! || GET_CODE (op1) == NEG)
return CCLmode;
if (GET_CODE (op0) == AND)
--- 377,385 ----
if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
&& CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K'))
return CCAPmode;
! if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
! || GET_CODE (op1) == NEG)
! && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
return CCLmode;
if (GET_CODE (op0) == AND)
*************** s390_select_ccmode (code, op0, op1)
*** 432,438 ****
case LTU:
case GEU:
! if (GET_CODE (op0) == PLUS)
return CCL1mode;
if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
--- 433,440 ----
case LTU:
case GEU:
! if (GET_CODE (op0) == PLUS
! && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
return CCL1mode;
if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
*************** s390_select_ccmode (code, op0, op1)
*** 442,448 ****
case LEU:
case GTU:
! if (GET_CODE (op0) == MINUS)
return CCL2mode;
if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
--- 444,451 ----
case LEU:
case GTU:
! if (GET_CODE (op0) == MINUS
! && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
return CCL2mode;
if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
Index: gcc/config/s390/s390.md
===================================================================
RCS file: /cvsroot/gcc/gcc/gcc/config/s390/s390.md,v
retrieving revision 1.64
diff -p -c -r1.64 s390.md
*** gcc/config/s390/s390.md 22 Jul 2003 17:38:14 -0000 1.64
--- gcc/config/s390/s390.md 31 Jul 2003 14:13:21 -0000
***************
*** 3493,3498 ****
--- 3493,3525 ----
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd,fsimpd")])
+ (define_insn "*adddf3_cc"
+ [(set (reg 33)
+ (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:DF 2 "general_operand" "f,R"))
+ (match_operand:DF 3 "const0_operand" "")))
+ (set (match_operand:DF 0 "register_operand" "=f,f")
+ (plus:DF (match_dup 1) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IEEE_FLOAT"
+ "@
+ adbr\\t%0,%2
+ adb\\t%0,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsimpd,fsimpd")])
+
+ (define_insn "*adddf3_cconly"
+ [(set (reg 33)
+ (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:DF 2 "general_operand" "f,R"))
+ (match_operand:DF 3 "const0_operand" "")))
+ (clobber (match_scratch:DF 0 "=f,f"))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IEEE_FLOAT"
+ "@
+ adbr\\t%0,%2
+ adb\\t%0,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsimpd,fsimpd")])
+
(define_insn "*adddf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
***************
*** 3530,3535 ****
--- 3557,3589 ----
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps,fsimps")])
+ (define_insn "*addsf3_cc"
+ [(set (reg 33)
+ (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:SF 2 "general_operand" "f,R"))
+ (match_operand:SF 3 "const0_operand" "")))
+ (set (match_operand:SF 0 "register_operand" "=f,f")
+ (plus:SF (match_dup 1) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IEEE_FLOAT"
+ "@
+ aebr\\t%0,%2
+ aeb\\t%0,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsimps,fsimps")])
+
+ (define_insn "*addsf3_cconly"
+ [(set (reg 33)
+ (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:SF 2 "general_operand" "f,R"))
+ (match_operand:SF 3 "const0_operand" "")))
+ (clobber (match_scratch:SF 0 "=f,f"))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IEEE_FLOAT"
+ "@
+ aebr\\t%0,%2
+ aeb\\t%0,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsimps,fsimps")])
+
(define_insn "*addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
***************
*** 3794,3799 ****
--- 3848,3880 ----
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd,fsimpd")])
+ (define_insn "*subdf3_cc"
+ [(set (reg 33)
+ (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:DF 2 "general_operand" "f,R"))
+ (match_operand:DF 3 "const0_operand" "")))
+ (set (match_operand:DF 0 "register_operand" "=f,f")
+ (plus:DF (match_dup 1) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IEEE_FLOAT"
+ "@
+ sdbr\\t%0,%2
+ sdb\\t%0,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsimpd,fsimpd")])
+
+ (define_insn "*subdf3_cconly"
+ [(set (reg 33)
+ (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:DF 2 "general_operand" "f,R"))
+ (match_operand:DF 3 "const0_operand" "")))
+ (clobber (match_scratch:DF 0 "=f,f"))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IEEE_FLOAT"
+ "@
+ sdbr\\t%0,%2
+ sdb\\t%0,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsimpd,fsimpd")])
+
(define_insn "*subdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
***************
*** 3831,3836 ****
--- 3912,3944 ----
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps,fsimps")])
+ (define_insn "*subsf3_cc"
+ [(set (reg 33)
+ (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:SF 2 "general_operand" "f,R"))
+ (match_operand:SF 3 "const0_operand" "")))
+ (set (match_operand:SF 0 "register_operand" "=f,f")
+ (minus:SF (match_dup 1) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IEEE_FLOAT"
+ "@
+ sebr\\t%0,%2
+ seb\\t%0,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsimps,fsimps")])
+
+ (define_insn "*subsf3_cconly"
+ [(set (reg 33)
+ (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:SF 2 "general_operand" "f,R"))
+ (match_operand:SF 3 "const0_operand" "")))
+ (clobber (match_scratch:SF 0 "=f,f"))]
+ "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IEEE_FLOAT"
+ "@
+ sebr\\t%0,%2
+ seb\\t%0,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsimps,fsimps")])
+
(define_insn "*subsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0")
***************
*** 5384,5389 ****
--- 5492,5543 ----
"lper\\t%0,%1"
[(set_attr "op_type" "RR")
(set_attr "type" "fsimps")])
+
+ ;;
+ ;;- Negated absolute value instructions
+ ;;
+
+ ;
+ ; Integer
+ ;
+
+ (define_insn "*negabssi2"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))))
+ (clobber (reg:CC 33))]
+ ""
+ "lnr\\t%0,%1"
+ [(set_attr "op_type" "RR")])
+
+ (define_insn "*negabsdi2"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))))
+ (clobber (reg:CC 33))]
+ "TARGET_64BIT"
+ "lngr\\t%0,%1"
+ [(set_attr "op_type" "RRE")])
+
+ ;
+ ; Floating point
+ ;
+
+ (define_insn "*negabssf2"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
+ (clobber (reg:CC 33))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "lnebr\\t%0,%1"
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimps")])
+
+ (define_insn "*negabsdf2"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
+ (clobber (reg:CC 33))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "lndbr\\t%0,%1"
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimpd")])
;;
;;- Square root instructions.