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[PATCH] PR target/10979: ICE with atan2 intrinsic on x86 (take 2)
- From: Roger Sayle <roger at eyesopen dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Richard Henderson <rth at redhat dot com>
- Date: Fri, 4 Jul 2003 20:16:05 -0600 (MDT)
- Subject: [PATCH] PR target/10979: ICE with atan2 intrinsic on x86 (take 2)
On Wed, 2 Jul 2003, Richard Henderson wrote:
> On Mon, Jun 30, 2003 at 06:42:19AM -0600, Roger Sayle wrote:
> > The problem is that the middle end, places local floating point
> > variables into named pseudos, that expand_builtin_mathfn_2 then
> > passes directly to expand_binop, where gen_atan2df3 wraps one of
> > them in a clobber. Any attempt to use that local after the call
> > to atan2 then results in bad things; life gets very confused and
> > reg-stack eventually dies.
>
> The bug, IMO, is in gen_atan2df3. It ought to generate the new
> pseudo when necessary.
The following patch implements Richard Henderson's suggestion that
its better to fix this problem in i386.md's gen_atan2df3. We wrap
the original define_insns for fpatan with define_expand patterns,
renaming the instructions themselves to atan2?f3_1. These wrappers
make a copy of clobbered operand, and avoid the current ICE. This
achieves the same affect as the original patch, without the overhead
to other platforms or to the other mathematical builtins on x86.
This revised patch has been tested on i686-pc-linux-gnu with a full
"make bootstrap", all languages except Ada and treelang, and regression
tested with a top-level "make -k check".
Ok for mainline?
2003-07-04 Roger Sayle <roger@eyesopen.com>
PR target/10979
* config/i386/i386.md (atan2df3, atan2sf3, atan2xf3, atan2tf3):
Changed to define_expand patterns that copy operand[1] to prevent
it from being clobbered before emitting an atan2?f3_1 insn.
(atan2df3_1, atan2sf3_1, atan2xf_1, atan2tf3_1): New define_insn
patterns that actually specify the behaviour of x87's FPATAN.
* gcc.dg/20030630-1.c: New testcase.
Index: i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.474
diff -c -3 -p -r1.474 i386.md
*** i386.md 30 Jun 2003 13:39:03 -0000 1.474
--- i386.md 4 Jul 2003 13:23:09 -0000
***************
*** 15582,15588 ****
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
! (define_insn "atan2df3"
[(parallel [(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 2 "register_operand" "0")
(match_operand:DF 1 "register_operand" "u")]
--- 15582,15588 ----
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
! (define_insn "atan2df3_1"
[(parallel [(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 2 "register_operand" "0")
(match_operand:DF 1 "register_operand" "u")]
***************
*** 15594,15600 ****
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")])
! (define_insn "atan2sf3"
[(parallel [(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 2 "register_operand" "0")
(match_operand:SF 1 "register_operand" "u")]
--- 15594,15613 ----
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")])
! (define_expand "atan2df3"
! [(use (match_operand:DF 0 "register_operand" "=f"))
! (use (match_operand:DF 2 "register_operand" "0"))
! (use (match_operand:DF 1 "register_operand" "u"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
! {
! rtx copy = gen_reg_rtx (DFmode);
! emit_move_insn (copy, operands[1]);
! emit_insn (gen_atan2df3_1 (operands[0], copy, operands[2]));
! DONE;
! }
!
! (define_insn "atan2sf3_1"
[(parallel [(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 2 "register_operand" "0")
(match_operand:SF 1 "register_operand" "u")]
***************
*** 15606,15624 ****
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")])
! (define_insn "atan2xf3"
[(parallel [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 2 "register_operand" "0")
(match_operand:XF 1 "register_operand" "u")]
UNSPEC_FPATAN))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
! (define_insn "atan2tf3"
[(parallel [(set (match_operand:TF 0 "register_operand" "=f")
(unspec:TF [(match_operand:TF 2 "register_operand" "0")
(match_operand:TF 1 "register_operand" "u")]
--- 15619,15663 ----
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")])
! (define_expand "atan2sf3"
! [(use (match_operand:SF 0 "register_operand" "=f"))
! (use (match_operand:SF 2 "register_operand" "0"))
! (use (match_operand:SF 1 "register_operand" "u"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
! {
! rtx copy = gen_reg_rtx (SFmode);
! emit_move_insn (copy, operands[1]);
! emit_insn (gen_atan2sf3_1 (operands[0], copy, operands[2]));
! DONE;
! }
!
! (define_insn "atan2xf3_1"
[(parallel [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 2 "register_operand" "0")
(match_operand:XF 1 "register_operand" "u")]
UNSPEC_FPATAN))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && ! TARGET_128BIT_LONG_DOUBLE"
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
! (define_expand "atan2xf3"
! [(use (match_operand:XF 0 "register_operand" "=f"))
! (use (match_operand:XF 2 "register_operand" "0"))
! (use (match_operand:XF 1 "register_operand" "u"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && ! TARGET_128BIT_LONG_DOUBLE"
! {
! rtx copy = gen_reg_rtx (XFmode);
! emit_move_insn (copy, operands[1]);
! emit_insn (gen_atan2xf3_1 (operands[0], copy, operands[2]));
! DONE;
! }
!
! (define_insn "atan2tf3_1"
[(parallel [(set (match_operand:TF 0 "register_operand" "=f")
(unspec:TF [(match_operand:TF 2 "register_operand" "0")
(match_operand:TF 1 "register_operand" "u")]
***************
*** 15629,15634 ****
--- 15668,15686 ----
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
+
+ (define_expand "atan2tf3"
+ [(use (match_operand:TF 0 "register_operand" "=f"))
+ (use (match_operand:TF 2 "register_operand" "0"))
+ (use (match_operand:TF 1 "register_operand" "u"))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
+ {
+ rtx copy = gen_reg_rtx (TFmode);
+ emit_move_insn (copy, operands[1]);
+ emit_insn (gen_atan2tf3_1 (operands[0], copy, operands[2]));
+ DONE;
+ }
(define_insn "*fyl2x_sfxf3"
[(parallel [(set (match_operand:SF 0 "register_operand" "=f")
/* Derived from PR target/10979. */
/* This testcase used to ICE on x86. */
/* { dg-do compile } */
/* { dg-options "-O2 -ffast-math" } */
void t(double);
double atan2(double,double);
void temp(double *c)
{
double c2 = 8;
double s2 = 0;
*c = atan2(s2,c2);
t(1/s2);
}
Roger
--
Roger Sayle, E-mail: roger@eyesopen.com
OpenEye Scientific Software, WWW: http://www.eyesopen.com/
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