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[patch] config/i*: Fix comment typos.
- From: Kazu Hirata <kazu at cs dot umass dot edu>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 02 Jul 2003 17:34:04 -0400 (EDT)
- Subject: [patch] config/i*: Fix comment typos.
Hi,
Attached is a patch to fix comment typos. Committed as obvious.
Kazu Hirata
2003-07-02 Kazu Hirata <kazu@cs.umass.edu>
* config/i386/emmintrin.h: Fix comment typos.
* config/i386/i386.c: Likewise.
* config/i386/i386.h: Likewise.
* config/i386/sco5.h: Likewise.
* config/ia64/ia64.c: Likewise.
* config/ia64/itanium2.md: Likewise.
Index: config/i386/emmintrin.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/emmintrin.h,v
retrieving revision 1.1
diff -u -r1.1 emmintrin.h
--- config/i386/emmintrin.h 6 Jun 2003 13:52:17 -0000 1.1
+++ config/i386/emmintrin.h 2 Jul 2003 21:27:28 -0000
@@ -147,7 +147,7 @@
__builtin_ia32_storesd (__P, (__v2df)__A);
}
-/* Store the lower DPFP value acrosd two words. */
+/* Store the lower DPFP value across two words. */
static __inline void
_mm_store1_pd (double *__P, __m128d __A)
{
Index: config/i386/i386.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.c,v
retrieving revision 1.582
diff -u -r1.582 i386.c
--- config/i386/i386.c 30 Jun 2003 07:57:58 -0000 1.582
+++ config/i386/i386.c 2 Jul 2003 21:27:34 -0000
@@ -2608,7 +2608,7 @@
if (AGGREGATE_TYPE_P (type))
{
- /* Walk the agregates recursivly. */
+ /* Walk the agregates recursively. */
if (TREE_CODE (type) == RECORD_TYPE
|| TREE_CODE (type) == UNION_TYPE
|| TREE_CODE (type) == QUAL_UNION_TYPE)
@@ -9597,9 +9597,9 @@
code = swap_condition (code);
}
- /* Try to expand the comparsion and verify that we end up with carry flag
- based comparsion. This is fails to be true only when we decide to expand
- comparsion using arithmetic that is not too common scenario. */
+ /* Try to expand the comparison and verify that we end up with carry flag
+ based comparison. This is fails to be true only when we decide to expand
+ comparison using arithmetic that is not too common scenario. */
start_sequence ();
compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
&second_test, &bypass_test);
@@ -12217,7 +12217,7 @@
floating unit pipeline preparation stages, the memory operands
for floating point are cheaper.
- ??? For Athlon it the difference is most propbably 2. */
+ ??? For Athlon it the difference is most probably 2. */
if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
loadcost = 3;
else
@@ -15690,7 +15690,7 @@
/* We don't have exact information about the insn sizes, but we may assume
quite safely that we are informed about all 1 byte insns and memory
- address sizes. This is enought to elliminate unnecesary padding in
+ address sizes. This is enough to eliminate unnecessary padding in
99% of cases. */
static int
@@ -15735,7 +15735,7 @@
return 2;
}
-/* AMD K8 core misspredicts jumps when there are more than 3 jumps in 16 byte
+/* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
window. */
static void
@@ -15839,7 +15839,7 @@
&& ((GET_CODE (prev) == JUMP_INSN && any_condjump_p (prev))
|| GET_CODE (prev) == CALL_INSN))
replace = true;
- /* Empty functions get branch misspredict even when the jump destination
+ /* Empty functions get branch mispredict even when the jump destination
is not visible to us. */
if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
replace = true;
Index: config/i386/i386.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.h,v
retrieving revision 1.348
diff -u -r1.348 i386.h
--- config/i386/i386.h 26 Jun 2003 06:13:27 -0000 1.348
+++ config/i386/i386.h 2 Jul 2003 21:27:36 -0000
@@ -1248,7 +1248,7 @@
#define RETURN_IN_MEMORY(TYPE) \
ix86_return_in_memory (TYPE)
-/* This is overriden by <cygwin.h>. */
+/* This is overridden by <cygwin.h>. */
#define MS_AGGREGATE_RETURN 0
Index: config/i386/sco5.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/sco5.h,v
retrieving revision 1.79
diff -u -r1.79 sco5.h
--- config/i386/sco5.h 19 Jun 2003 21:47:12 -0000 1.79
+++ config/i386/sco5.h 2 Jul 2003 21:27:37 -0000
@@ -36,7 +36,7 @@
* Here's the reason why. If we dont define them, and we dont define them
* to always emit to the same section, the default is to emit to "named"
* ctors and dtors sections. This would be great if we could use GNU ld,
- * but we can't. The native linker could possibly be trained to coallesce
+ * but we can't. The native linker could possibly be trained to coalesce
* named ctors sections, but that hasn't been done either. So if we don't
* define these, many C++ ctors and dtors dont get run, because they never
* wind up in the ctors/dtors arrays.
Index: config/ia64/ia64.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/ia64.c,v
retrieving revision 1.234
diff -u -r1.234 ia64.c
--- config/ia64/ia64.c 27 Jun 2003 09:49:40 -0000 1.234
+++ config/ia64/ia64.c 2 Jul 2003 21:27:40 -0000
@@ -4268,7 +4268,7 @@
break;
case FR_REGS:
- /* Need to go through general regsters to get to other class regs. */
+ /* Need to go through general registers to get to other class regs. */
if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
return GR_REGS;
Index: config/ia64/itanium2.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/itanium2.md,v
retrieving revision 1.3
diff -u -r1.3 itanium2.md
--- config/ia64/itanium2.md 13 Mar 2003 18:26:30 -0000 1.3
+++ config/ia64/itanium2.md 2 Jul 2003 21:27:41 -0000
@@ -484,7 +484,7 @@
(define_reservation "2_M_only_um01" "2_M0_only_um01|2_M1_only_um01")
;; I instruction is dispersed to the lowest numbered I unit
-;; not already in use. Remeber about possible spliting.
+;; not already in use. Remeber about possible splitting.
(define_reservation "2_I0"
"2_0mi.i+2_ui0|2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0\
|2_0mfi.+2_ui0|2_0mi.b+2_ui0|(2_1mi.i|2_1mi.b)+(2_ui0|2_ui1)\
@@ -1335,7 +1335,7 @@
+(2b_um2|2b_um3)")
;; I instruction is dispersed to the lowest numbered I unit
-;; not already in use. Remeber about possible spliting.
+;; not already in use. Remeber about possible splitting.
(define_reservation "2b_I"
"2b_0mi.i+2_2+2b_ui0|2b_0mii.+2_3+(2b_ui0|2b_ui1)|2b_0mmi.+2_3+2b_ui0\
|2b_0mfi.+2_3+2b_ui0|2b_0mi.b+2_2+2b_ui0\