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[patch] config/a*: Fix comment typos.
- From: Kazu Hirata <kazu at cs dot umass dot edu>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 01 Jul 2003 19:26:49 -0400 (EDT)
- Subject: [patch] config/a*: Fix comment typos.
Hi,
Attached is a patch to fix comment typos. Committed as obvious.
Kazu Hirata
2003-07-01 Kazu Hirata <kazu@cs.umass.edu>
* config/alpha/alpha.c: Fix comment typos.
* config/alpha/elf.h: Likewise.
* config/arm/arm.c: Likewise.
* config/arm/arm.h: Likewise.
* config/arm/arm.md: Likewise.
* config/arm/t-arm-coff: Likewise.
* config/arm/t-strongarm-pe: Likewise.
* config/arm/xscale-elf.h: Likewise.
* config/avr/avr.h: Likewise.
Index: config/alpha/alpha.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.c,v
retrieving revision 1.320
diff -u -r1.320 alpha.c
--- config/alpha/alpha.c 27 Jun 2003 17:52:03 -0000 1.320
+++ config/alpha/alpha.c 1 Jul 2003 23:19:25 -0000
@@ -974,7 +974,7 @@
{
if (TARGET_ABI_OSF)
{
- /* Disallow virtual registers to cope with pathalogical test cases
+ /* Disallow virtual registers to cope with pathological test cases
such as compile/930117-1.c in which the virtual reg decomposes
to the frame pointer. Which is a hard reg that is not $27. */
return (REGNO (op) == 27 || REGNO (op) > LAST_VIRTUAL_REGISTER);
@@ -2006,7 +2006,7 @@
that we've marked with gpdisp relocs, since those have to stay in
1-1 correspondence with one another.
- Techinically we could copy them if we could set up a mapping from one
+ Technically we could copy them if we could set up a mapping from one
sequence number to another, across the set of insns to be duplicated.
This seems overly complicated and error-prone since interblock motion
from sched-ebb could move one of the pair of insns to a different block. */
@@ -7253,7 +7253,7 @@
=> alpha_procedure_type != PT_NULL,
so when we are not setting the bit here, we are guaranteed to
- have emited an FRP frame pointer update just before. */
+ have emitted an FRP frame pointer update just before. */
RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed;
}
}
@@ -8267,7 +8267,7 @@
}
/* Alpha can only issue instruction groups simultaneously if they are
- suitibly aligned. This is very processor-specific. */
+ suitably aligned. This is very processor-specific. */
enum alphaev4_pipe {
EV4_STOP = 0,
@@ -8857,7 +8857,7 @@
unsigned HOST_WIDE_INT align)
{
if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value)
- /* ??? Consider using mergable sdata sections. */
+ /* ??? Consider using mergeable sdata sections. */
sdata_section ();
else
default_elf_select_rtx_section (mode, x, align);
Index: config/alpha/elf.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/elf.h,v
retrieving revision 1.71
diff -u -r1.71 elf.h
--- config/alpha/elf.h 19 Jun 2003 21:47:03 -0000 1.71
+++ config/alpha/elf.h 1 Jul 2003 23:19:26 -0000
@@ -149,7 +149,7 @@
not defined, the default value is `BIGGEST_ALIGNMENT'.
This value is really 2^63. Since gcc figures the alignment in bits,
- we could only potentially get to 2^60 on suitible hosts. Due to other
+ we could only potentially get to 2^60 on suitable hosts. Due to other
considerations in varasm, we must restrict this to what fits in an int. */
#undef MAX_OFILE_ALIGNMENT
Index: config/arm/arm.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.c,v
retrieving revision 1.287
diff -u -r1.287 arm.c
--- config/arm/arm.c 30 Jun 2003 12:06:04 -0000 1.287
+++ config/arm/arm.c 1 Jul 2003 23:19:31 -0000
@@ -2085,7 +2085,7 @@
tree t;
/* Maintain 64-bit alignment of the valist pointer by
- contructing: valist = ((valist + (8 - 1)) & -8). */
+ constructing: valist = ((valist + (8 - 1)) & -8). */
minus_eight = build_int_2 (- (IWMMXT_ALIGNMENT / BITS_PER_UNIT), -1);
t = build_int_2 ((IWMMXT_ALIGNMENT / BITS_PER_UNIT) - 1, 0);
t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
@@ -6124,7 +6124,7 @@
/* Move a minipool fix MP from its current location to before MAX_MP.
If MAX_MP is NULL, then MP doesn't need moving, but the addressing
- contrains may need updating. */
+ constraints may need updating. */
static Mnode *
move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
HOST_WIDE_INT max_address)
@@ -6747,7 +6747,7 @@
Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
#ifdef AOF_ASSEMBLER
- /* PIC symbol refereneces need to be converted into offsets into the
+ /* PIC symbol references need to be converted into offsets into the
based area. */
/* XXX This shouldn't be done here. */
if (flag_pic && GET_CODE (value) == SYMBOL_REF)
@@ -9490,13 +9490,13 @@
In a pair of registers containing a DI or DF value the 'Q'
operand returns the register number of the register containing
- the least signficant part of the value. The 'R' operand returns
+ the least significant part of the value. The 'R' operand returns
the register number of the register containing the most
significant part of the value.
The 'H' operand returns the higher of the two register numbers.
On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
- same as the 'Q' operand, since the most signficant part of the
+ same as the 'Q' operand, since the most significant part of the
value is held in the lower number register. The reverse is true
on systems where WORDS_BIG_ENDIAN is false.
@@ -11702,7 +11702,7 @@
high_regs_pushed++;
/* The prolog may have pushed some high registers to use as
- work registers. eg the testuite file:
+ work registers. eg the testsuite file:
gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
compiles to produce:
push {r4, r5, r6, r7, lr}
Index: config/arm/arm.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.h,v
retrieving revision 1.201
diff -u -r1.201 arm.h
--- config/arm/arm.h 30 Jun 2003 13:17:38 -0000 1.201
+++ config/arm/arm.h 1 Jul 2003 23:19:34 -0000
@@ -1024,7 +1024,7 @@
/* The number of (integer) argument register available. */
#define NUM_ARG_REGS 4
-/* Return the regiser number of the N'th (integer) argument. */
+/* Return the register number of the N'th (integer) argument. */
#define ARG_REGISTER(N) (N - 1)
#if 0 /* FIXME: The ARM backend has special code to handle structure
Index: config/arm/arm.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.md,v
retrieving revision 1.138
diff -u -r1.138 arm.md
--- config/arm/arm.md 22 Jun 2003 13:54:38 -0000 1.138
+++ config/arm/arm.md 1 Jul 2003 23:19:36 -0000
@@ -1726,7 +1726,7 @@
/* A Trick, since we are setting the bottom bits in the word,
we can shift operand[3] up, operand[0] down, OR them together
and rotate the result back again. This takes 3 insns, and
- the third might be mergable into another op. */
+ the third might be mergeable into another op. */
/* The shift up copes with the possibility that operand[3] is
wider than the bitfield. */
rtx op0 = gen_reg_rtx (SImode);
Index: config/arm/t-arm-coff
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/t-arm-coff,v
retrieving revision 1.3
diff -u -r1.3 t-arm-coff
--- config/arm/t-arm-coff 17 May 2001 03:15:48 -0000 1.3
+++ config/arm/t-arm-coff 1 Jul 2003 23:19:36 -0000
@@ -28,7 +28,7 @@
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
-# Currently there is a bug somwehere in GCC's alias analysis
+# Currently there is a bug somewhere in GCC's alias analysis
# or scheduling code that is breaking _fpmul_parts in fp-bit.c.
# Disabling function inlining is a workaround for this problem.
TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline
Index: config/arm/t-strongarm-pe
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/t-strongarm-pe,v
retrieving revision 1.3
diff -u -r1.3 t-strongarm-pe
--- config/arm/t-strongarm-pe 16 Dec 2002 18:20:57 -0000 1.3
+++ config/arm/t-strongarm-pe 1 Jul 2003 23:19:36 -0000
@@ -32,7 +32,7 @@
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
-# Currently there is a bug somwehere in GCC's alias analysis
+# Currently there is a bug somewhere in GCC's alias analysis
# or scheduling code that is breaking _fpmul_parts in fp-bit.c.
# Disabling function inlining is a workaround for this problem.
TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline
Index: config/arm/xscale-elf.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/xscale-elf.h,v
retrieving revision 1.6
diff -u -r1.6 xscale-elf.h
--- config/arm/xscale-elf.h 9 Apr 2003 15:14:23 -0000 1.6
+++ config/arm/xscale-elf.h 1 Jul 2003 23:19:36 -0000
@@ -32,7 +32,7 @@
the assembler:
-mfpu=softvfp This is the default. It indicates thats doubles are
- stored in a format compatable with the VFP
+ stored in a format compatible with the VFP
specification. This is the newer double format, whereby
the endian-ness of the doubles matches the endian-ness
of the memory architecture.
@@ -43,8 +43,8 @@
is what happens].
-mfpu=softfpa This is when -msoft-float is specified.
- This is the normal beahviour of other arm configurations,
- which for backwards compatability purposes default to
+ This is the normal behavior of other arm configurations,
+ which for backwards compatibility purposes default to
supporting the old FPA format which was always big
endian, regardless of the endian-ness of the memory
system. */
Index: config/avr/avr.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/avr/avr.h,v
retrieving revision 1.87
diff -u -r1.87 avr.h
--- config/avr/avr.h 26 Jun 2003 13:11:09 -0000 1.87
+++ config/avr/avr.h 1 Jul 2003 23:19:38 -0000
@@ -364,7 +364,7 @@
One use of this macro is on machines where the highest numbered
registers must always be saved and the save-multiple-registers
- instruction supports only sequences of consetionve registers. On
+ instruction supports only sequences of consecutive registers. On
such machines, define `REG_ALLOC_ORDER' to be an initializer that
lists the highest numbered allocatable register first. */