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Re: RFA: reload bug fix (take 4) (Was: Re: RFC: reloading sums)
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: Joern Rennecke <joern dot rennecke at superh dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Tue, 01 Jul 2003 15:11:21 -0400
- Subject: Re: RFA: reload bug fix (take 4) (Was: Re: RFC: reloading sums)
- References: <3F01A5B4.7577AF89@superh.com>
I have committed the following patch.
2003-07-01 David Edelsohn <edelsohn@gnu.org>
J"orn Rennecke <joern.rennecke@superh.com>
* config/rs6000/rs6000.md (ctr{s,d}i_internal?): Add earlyclobber
for MEM case.
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.260
diff -c -p -r1.260 rs6000.md
*** rs6000.md 29 Jun 2003 04:24:55 -0000 1.260
--- rs6000.md 1 Jul 2003 18:42:45 -0000
***************
*** 13989,14003 ****
(define_insn "*ctrsi_internal1"
[(set (pc)
! (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
! (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
(plus:SI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x"))
! (clobber (match_scratch:SI 4 "=X,X,r"))]
"! TARGET_POWERPC64"
"*
{
--- 13989,14003 ----
(define_insn "*ctrsi_internal1"
[(set (pc)
! (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
! (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
(plus:SI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
! (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
"! TARGET_POWERPC64"
"*
{
***************
*** 14009,14027 ****
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrsi_internal2"
[(set (pc)
! (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
(const_int 1))
(pc)
(label_ref (match_operand 0 "" ""))))
! (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
(plus:SI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x"))
! (clobber (match_scratch:SI 4 "=X,X,r"))]
"! TARGET_POWERPC64"
"*
{
--- 14009,14027 ----
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16,16")])
(define_insn "*ctrsi_internal2"
[(set (pc)
! (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
(const_int 1))
(pc)
(label_ref (match_operand 0 "" ""))))
! (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
(plus:SI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
! (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
"! TARGET_POWERPC64"
"*
{
***************
*** 14033,14051 ****
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrdi_internal1"
[(set (pc)
! (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
! (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x"))
! (clobber (match_scratch:DI 4 "=X,X,r"))]
"TARGET_POWERPC64"
"*
{
--- 14033,14051 ----
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16,16")])
(define_insn "*ctrdi_internal1"
[(set (pc)
! (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
! (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
! (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
"TARGET_POWERPC64"
"*
{
***************
*** 14057,14075 ****
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrdi_internal2"
[(set (pc)
! (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 1))
(pc)
(label_ref (match_operand 0 "" ""))))
! (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x"))
! (clobber (match_scratch:DI 4 "=X,X,r"))]
"TARGET_POWERPC64"
"*
{
--- 14057,14075 ----
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16,16")])
(define_insn "*ctrdi_internal2"
[(set (pc)
! (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
(const_int 1))
(pc)
(label_ref (match_operand 0 "" ""))))
! (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
! (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
"TARGET_POWERPC64"
"*
{
***************
*** 14081,14101 ****
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
;; Similar, but we can use GE since we have a REG_NONNEG.
(define_insn "*ctrsi_internal3"
[(set (pc)
! (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
! (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
(plus:SI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&X"))
! (clobber (match_scratch:SI 4 "=X,X,r"))]
"! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
--- 14081,14101 ----
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16,16")])
;; Similar, but we can use GE since we have a REG_NONNEG.
(define_insn "*ctrsi_internal3"
[(set (pc)
! (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
! (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
(plus:SI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
! (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
"! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
***************
*** 14107,14125 ****
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrsi_internal4"
[(set (pc)
! (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
(const_int 0))
(pc)
(label_ref (match_operand 0 "" ""))))
! (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
(plus:SI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&X"))
! (clobber (match_scratch:SI 4 "=X,X,r"))]
"! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
--- 14107,14125 ----
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16,16")])
(define_insn "*ctrsi_internal4"
[(set (pc)
! (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
(const_int 0))
(pc)
(label_ref (match_operand 0 "" ""))))
! (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
(plus:SI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
! (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
"! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
***************
*** 14131,14149 ****
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrdi_internal3"
[(set (pc)
! (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
! (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x"))
! (clobber (match_scratch:DI 4 "=X,X,r"))]
"TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
--- 14131,14149 ----
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16,16")])
(define_insn "*ctrdi_internal3"
[(set (pc)
! (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
! (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
! (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
"TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
***************
*** 14155,14173 ****
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrdi_internal4"
[(set (pc)
! (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 0))
(pc)
(label_ref (match_operand 0 "" ""))))
! (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x"))
! (clobber (match_scratch:DI 4 "=X,X,r"))]
"TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
--- 14155,14173 ----
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16,16")])
(define_insn "*ctrdi_internal4"
[(set (pc)
! (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
(const_int 0))
(pc)
(label_ref (match_operand 0 "" ""))))
! (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
! (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
"TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
***************
*** 14179,14199 ****
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
;; Similar but use EQ
(define_insn "*ctrsi_internal5"
[(set (pc)
! (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
! (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
(plus:SI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x"))
! (clobber (match_scratch:SI 4 "=X,X,r"))]
"! TARGET_POWERPC64"
"*
{
--- 14179,14199 ----
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16,16")])
;; Similar but use EQ
(define_insn "*ctrsi_internal5"
[(set (pc)
! (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
! (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
(plus:SI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
! (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
"! TARGET_POWERPC64"
"*
{
***************
*** 14205,14223 ****
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrsi_internal6"
[(set (pc)
! (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
(const_int 1))
(pc)
(label_ref (match_operand 0 "" ""))))
! (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
(plus:SI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x"))
! (clobber (match_scratch:SI 4 "=X,X,r"))]
"! TARGET_POWERPC64"
"*
{
--- 14205,14223 ----
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16,16")])
(define_insn "*ctrsi_internal6"
[(set (pc)
! (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
(const_int 1))
(pc)
(label_ref (match_operand 0 "" ""))))
! (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
(plus:SI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
! (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
"! TARGET_POWERPC64"
"*
{
***************
*** 14229,14247 ****
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrdi_internal5"
[(set (pc)
! (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
! (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x"))
! (clobber (match_scratch:DI 4 "=X,X,r"))]
"TARGET_POWERPC64"
"*
{
--- 14229,14247 ----
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16,16")])
(define_insn "*ctrdi_internal5"
[(set (pc)
! (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
! (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
! (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
"TARGET_POWERPC64"
"*
{
***************
*** 14253,14271 ****
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrdi_internal6"
[(set (pc)
! (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 1))
(pc)
(label_ref (match_operand 0 "" ""))))
! (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x"))
! (clobber (match_scratch:DI 4 "=X,X,r"))]
"TARGET_POWERPC64"
"*
{
--- 14253,14271 ----
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16,16")])
(define_insn "*ctrdi_internal6"
[(set (pc)
! (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
(const_int 1))
(pc)
(label_ref (match_operand 0 "" ""))))
! (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
! (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
! (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
"TARGET_POWERPC64"
"*
{
***************
*** 14277,14283 ****
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
;; Now the splitters if we could not allocate the CTR register
--- 14277,14283 ----
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16,16")])
;; Now the splitters if we could not allocate the CTR register