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S/390: Add z990 long displacement support
- From: Ulrich Weigand <weigand at i1 dot informatik dot uni-erlangen dot de>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 1 Jul 2003 00:13:00 +0200 (MET DST)
- Subject: S/390: Add z990 long displacement support
Hello,
this patch adds support for the new and modified instructions
added by the z990 long-displacement facility which provides
memory addressing using a 20-bit signed displacement in addition to
(or replacing) the previous 12-bit unsigned displacement.
Also, a new LOAD BYTE instruction was added.
To make use of the new instructions, binutils support is
required as well.
Bootstrapped/regtested on s390-ibm-linux, s390x-ibm-linux,
and s390x-ibm-linux with --with-arch=z990 (together with
the previous z990 instruction scheduling patch).
Bye,
Ulrich
ChangeLog:
* config/s390/s390.c (s390_extra_constraint): New function.
* config/s390/s390-protos.h (s390_extra_constraint): Declare it.
* config/s390/s390.h (EXTRA_CONSTRAINT): Use it.
* config/s390/s390.c (q_constraint): Remove.
* config/s390/s390-protos.h (q_constraint): Likewise.
* config/s390/s390.h (EXTRA_MEMORY_CONSTRAINT): Add 'R', 'S', 'T'.
(EXTRA_ADDRESS_CONSTRAINT): Define.
* config/s390/s390.c (larl_operand): Refuse out-of-range operands.
(DISP_IN_RANGE, s390_short_displacement): New.
(legitimate_reload_operand_p): Support long displacements.
(s390_decompose_address): Likewise.
(legitimize_pic_address): Likewise.
(legitimize_address): Likewise.
(s390_fixup_clobbered_return_reg): Likewise.
(s390_emit_prologue, s390_emit_epilogue): Likewise.
(s390_output_mi_thunk): Likewise.
* config/s390/s390.md (attr "op_type): Add "RXY", "RSY", "SIY".
(attr "atype", attr "length"): Add defaults for new op_types.
(all insns): Change op_type attribute where appropriate.
("*movdi_lay", "*movsi_lay", "*extendqidi2", "*extendqisi2"): New insns.
("*tmqi_ext", "*tmdi_mem", "*tmsi_mem", "*tmhi_mem", *tmqi_mem",
"*tstsi", "*tstsi_cconly", "*tsthiCCT", "*tsthiCCT_cconly",
"*tsthi", "*tsthi_cconly", "*tstqiCCT", "*tstqiCCT_cconly",
"*tstqi", "*tstqi_cconly", "*cmpsi_ccs_sign", "*cmpsi_ccs",
"*cmpsi_ccu", "*cmphi_ccu", "*cmpqi_ccu", "*cli",
"movti", "*movdi_64", "*movdi_31", "*movsi", "movhi", "movqi_64",
"movqi", "*movstrictqi", "*movstricthi", "movstrictsi",
"*movdf_64", "*movdf_31", "*movsf",
"*load_multiple_si", "*store_multiple_di",
"*sethighqisi", "*sethighhisi", "*sethighqidi_31", "*extendhisi2",
"*la_64", "*la_31", "*la_31_and", "force_la_31",
"*addsi3_carry1_cc", *addsi3_carry1_cconly",
"*addsi3_carry2_cc", *addsi3_carry2_cconly",
"*addsi3_cc", "*addsi3_cconly", "*addsi3_cconly2",
"*addsi3_sign", "*addsi3_sub", "addsi3",
"*subsi3_borrow_cc", "*subsi3_borrow_cconly", "*subsi3_cc",
"*subsi3_cconly", "*subsi3_sign", "*subsi3_sub", "subsi3",
"mulsi3"
"*andsi3_cc", "*andsi3_cconly", "andsi3",
"*andqi3_ss", "*andqi3_ss_inv",
"*iorsi3_cc", "*iorsi3_cconly", "iorsi3",
"*iorqi3_ss", "*iorqi3_ss_inv",
"*xorsi3_cc", "*xorsi3_cconly", "xorsi3",
"*xorqi3_ss", "*xorqi3_ss_inv",
"*tls_load_31"): Add alternatives for long-displacement instructions.
("*cmpdf_ccs", "*cmpdf_ccs_ibm", "*cmpsf_ccs", "*cmpsf_ccs_ibm",
"*load_multiple_di", "*store_multiple_di",
"*sethighqidi_64", "*zero_extendhisi2_31",
"truncdfsf2_ibm", "extendsfdf2_ieee", "extendsfdf2_ibm",
"adddf3", "*adddf3", "*adddf3_ibm",
"addsf3", "*addsf3", "*addsf3_ibm",
"subdf3", "*subdf3", "*subdf3_ibm",
"subsf3", "*subsf3", "*subsf3_ibm",
"mulsi_6432", "divmoddisi3",
"muldf3", "*muldf3", "*muldf3_ibm",
"mulsf3", "*mulsf3", "*mulsf3_ibm",
"divdf3", "*divdf3", "*divdf3_ibm",
"divsf3", "div*sf3", "*divsf3_ibm",
"sqrtdf2", "sqrtsf2",
"*cjump_long", "*icjump_long", "indirect_jump", "casesi_jump",
"*doloop_si_long", "*doloop_di_long", "bas_64", "bas_31",
"bas_r_64", "bas_r_31", "bas_tls_31", "bas_tls_64"): Adapt memory
and address constraints for instructions that do not accept long
displacements.
Index: gcc/config/s390/s390-protos.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390-protos.h,v
retrieving revision 1.30
diff -c -p -r1.30 s390-protos.h
*** gcc/config/s390/s390-protos.h 27 Jun 2003 21:10:13 -0000 1.30
--- gcc/config/s390/s390-protos.h 30 Jun 2003 22:02:42 -0000
*************** extern void s390_emit_epilogue PARAMS ((
*** 29,35 ****
extern void s390_function_profiler PARAMS ((FILE *, int));
#ifdef RTX_CODE
! extern int q_constraint PARAMS ((rtx));
extern int const0_operand PARAMS ((rtx, enum machine_mode));
extern int consttable_operand PARAMS ((rtx, enum machine_mode));
extern int larl_operand PARAMS ((rtx, enum machine_mode));
--- 29,35 ----
extern void s390_function_profiler PARAMS ((FILE *, int));
#ifdef RTX_CODE
! extern int s390_extra_constraint PARAMS ((rtx, int));
extern int const0_operand PARAMS ((rtx, enum machine_mode));
extern int consttable_operand PARAMS ((rtx, enum machine_mode));
extern int larl_operand PARAMS ((rtx, enum machine_mode));
Index: gcc/config/s390/s390.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.c,v
retrieving revision 1.99
diff -c -p -r1.99 s390.c
*** gcc/config/s390/s390.c 30 Jun 2003 22:01:00 -0000 1.99
--- gcc/config/s390/s390.c 30 Jun 2003 22:02:44 -0000
*************** static int s390_branch_condition_mask PA
*** 204,209 ****
--- 204,210 ----
static const char *s390_branch_condition_mnemonic PARAMS ((rtx, int));
static int check_mode PARAMS ((rtx, enum machine_mode *));
static int general_s_operand PARAMS ((rtx, enum machine_mode, int));
+ static int s390_short_displacement PARAMS ((rtx));
static int s390_decompose_address PARAMS ((rtx, struct s390_address *));
static rtx get_thread_pointer PARAMS ((void));
static rtx legitimize_tls_address PARAMS ((rtx, rtx));
*************** static rtx restore_gprs PARAMS ((rtx, in
*** 228,233 ****
--- 229,239 ----
static int s390_function_arg_size PARAMS ((enum machine_mode, tree));
static bool s390_function_arg_float PARAMS ((enum machine_mode, tree));
static struct machine_function * s390_init_machine_status PARAMS ((void));
+
+ /* Check whether integer displacement is in range. */
+ #define DISP_IN_RANGE(d) \
+ (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \
+ : ((d) >= 0 && (d) <= 4095))
/* Return true if SET either doesn't set the CC register, or else
the source and destination have matching CC modes and that
*************** larl_operand (op, mode)
*** 1103,1114 ****
return 0;
op = XEXP (op, 0);
! /* Allow adding *even* constants. */
if (GET_CODE (op) == PLUS)
{
if (GET_CODE (XEXP (op, 1)) != CONST_INT
|| (INTVAL (XEXP (op, 1)) & 1) != 0)
return 0;
op = XEXP (op, 0);
}
--- 1109,1125 ----
return 0;
op = XEXP (op, 0);
! /* Allow adding *even* in-range constants. */
if (GET_CODE (op) == PLUS)
{
if (GET_CODE (XEXP (op, 1)) != CONST_INT
|| (INTVAL (XEXP (op, 1)) & 1) != 0)
return 0;
+ #if HOST_BITS_PER_WIDE_INT > 32
+ if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 32
+ || INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 32))
+ return 0;
+ #endif
op = XEXP (op, 0);
}
*************** s_imm_operand (op, mode)
*** 1221,1244 ****
return general_s_operand (op, mode, 1);
}
! /* Return true if OP is a valid operand for a 'Q' constraint.
! This differs from s_operand in that only memory operands
! without index register are accepted, nothing else. */
int
! q_constraint (op)
! register rtx op;
{
struct s390_address addr;
! if (GET_CODE (op) != MEM)
! return 0;
! if (!s390_decompose_address (XEXP (op, 0), &addr))
! return 0;
! if (addr.indx)
! return 0;
return 1;
}
--- 1232,1352 ----
return general_s_operand (op, mode, 1);
}
! /* Return true if DISP is a valid short displacement. */
!
! static int
! s390_short_displacement (disp)
! rtx disp;
! {
! /* No displacement is OK. */
! if (!disp)
! return 1;
!
! /* Integer displacement in range. */
! if (GET_CODE (disp) == CONST_INT)
! return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
!
! /* GOT offset is not OK, the GOT can be large. */
! if (GET_CODE (disp) == CONST
! && GET_CODE (XEXP (disp, 0)) == UNSPEC
! && XINT (XEXP (disp, 0), 1) == 110)
! return 0;
!
! /* All other symbolic constants are literal pool references,
! which are OK as the literal pool must be small. */
! if (GET_CODE (disp) == CONST)
! return 1;
!
! return 0;
! }
!
! /* Return true if OP is a valid operand for a C constraint. */
int
! s390_extra_constraint (op, c)
! rtx op;
! int c;
{
struct s390_address addr;
! switch (c)
! {
! case 'Q':
! if (GET_CODE (op) != MEM)
! return 0;
! if (!s390_decompose_address (XEXP (op, 0), &addr))
! return 0;
! if (addr.indx)
! return 0;
! if (TARGET_LONG_DISPLACEMENT)
! {
! if (!s390_short_displacement (addr.disp))
! return 0;
! }
! break;
! case 'R':
! if (GET_CODE (op) != MEM)
! return 0;
!
! if (TARGET_LONG_DISPLACEMENT)
! {
! if (!s390_decompose_address (XEXP (op, 0), &addr))
! return 0;
! if (!s390_short_displacement (addr.disp))
! return 0;
! }
! break;
!
! case 'S':
! if (!TARGET_LONG_DISPLACEMENT)
! return 0;
! if (GET_CODE (op) != MEM)
! return 0;
! if (!s390_decompose_address (XEXP (op, 0), &addr))
! return 0;
! if (addr.indx)
! return 0;
! if (s390_short_displacement (addr.disp))
! return 0;
! break;
!
! case 'T':
! if (!TARGET_LONG_DISPLACEMENT)
! return 0;
! if (GET_CODE (op) != MEM)
! return 0;
! /* Any invalid address here will be fixed up by reload,
! so accept it for the most generic constraint. */
! if (s390_decompose_address (XEXP (op, 0), &addr)
! && s390_short_displacement (addr.disp))
! return 0;
! break;
!
! case 'U':
! if (TARGET_LONG_DISPLACEMENT)
! {
! if (!s390_decompose_address (op, &addr))
! return 0;
! if (!s390_short_displacement (addr.disp))
! return 0;
! }
! break;
!
! case 'W':
! if (!TARGET_LONG_DISPLACEMENT)
! return 0;
! /* Any invalid address here will be fixed up by reload,
! so accept it for the most generic constraint. */
! if (s390_decompose_address (op, &addr)
! && s390_short_displacement (addr.disp))
! return 0;
! break;
!
! default:
! return 0;
! }
return 1;
}
*************** int
*** 1673,1678 ****
--- 1781,1791 ----
legitimate_reload_constant_p (op)
register rtx op;
{
+ /* Accept la(y) operands. */
+ if (GET_CODE (op) == CONST_INT
+ && DISP_IN_RANGE (INTVAL (op)))
+ return 1;
+
/* Accept l(g)hi operands. */
if (GET_CODE (op) == CONST_INT
&& CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'))
*************** s390_decompose_address (addr, out)
*** 2016,2022 ****
this is fixed up by reload in any case. */
if (base != arg_pointer_rtx && indx != arg_pointer_rtx)
{
! if (INTVAL (disp) < 0 || INTVAL (disp) >= 4096)
return FALSE;
}
}
--- 2129,2135 ----
this is fixed up by reload in any case. */
if (base != arg_pointer_rtx && indx != arg_pointer_rtx)
{
! if (!DISP_IN_RANGE (INTVAL (disp)))
return FALSE;
}
}
*************** legitimize_pic_address (orig, reg)
*** 2395,2401 ****
pair of LARL and LA. */
rtx temp = reg? reg : gen_reg_rtx (Pmode);
! if (INTVAL (op1) < 0 || INTVAL (op1) >= 4096)
{
int even = INTVAL (op1) - 1;
op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
--- 2508,2514 ----
pair of LARL and LA. */
rtx temp = reg? reg : gen_reg_rtx (Pmode);
! if (!DISP_IN_RANGE (INTVAL (op1)))
{
int even = INTVAL (op1) - 1;
op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
*************** legitimize_address (x, oldx, mode)
*** 2766,2773 ****
change later anyway. */
if (GET_CODE (constant_term) == CONST_INT
! && (INTVAL (constant_term) < 0
! || INTVAL (constant_term) >= 4096)
&& !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
{
HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
--- 2879,2886 ----
change later anyway. */
if (GET_CODE (constant_term) == CONST_INT
! && !TARGET_LONG_DISPLACEMENT
! && !DISP_IN_RANGE (INTVAL (constant_term))
&& !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
{
HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
*************** s390_fixup_clobbered_return_reg (return_
*** 5050,5056 ****
reg = stack_pointer_rtx;
off = GEN_INT (cfun->machine->frame_size + REGNO (return_reg) * UNITS_PER_WORD);
! if (INTVAL (off) >= 4096)
{
off = force_const_mem (Pmode, off);
new_insn = gen_rtx_SET (Pmode, return_reg, off);
--- 5163,5169 ----
reg = stack_pointer_rtx;
off = GEN_INT (cfun->machine->frame_size + REGNO (return_reg) * UNITS_PER_WORD);
! if (!DISP_IN_RANGE (INTVAL (off)))
{
off = force_const_mem (Pmode, off);
new_insn = gen_rtx_SET (Pmode, return_reg, off);
*************** s390_emit_prologue ()
*** 5534,5544 ****
/* Substract frame size from stack pointer. */
! frame_off = GEN_INT (-cfun->machine->frame_size);
! if (!CONST_OK_FOR_LETTER_P (-cfun->machine->frame_size, 'K'))
! frame_off = force_const_mem (Pmode, frame_off);
- insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
RTX_FRAME_RELATED_P (insn) = 1;
REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
--- 5647,5667 ----
/* Substract frame size from stack pointer. */
! if (DISP_IN_RANGE (INTVAL (frame_off)))
! {
! insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
! gen_rtx_PLUS (Pmode, stack_pointer_rtx,
! frame_off));
! insn = emit_insn (insn);
! }
! else
! {
! if (!CONST_OK_FOR_LETTER_P (INTVAL (frame_off), 'K'))
! frame_off = force_const_mem (Pmode, frame_off);
!
! insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
! }
RTX_FRAME_RELATED_P (insn) = 1;
REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
*************** s390_emit_epilogue ()
*** 5697,5704 ****
{
/* Nothing to restore. */
}
! else if (cfun->machine->frame_size + area_bottom >= 0
! && cfun->machine->frame_size + area_top <= 4096)
{
/* Area is in range. */
offset = cfun->machine->frame_size;
--- 5820,5827 ----
{
/* Nothing to restore. */
}
! else if (DISP_IN_RANGE (cfun->machine->frame_size + area_bottom)
! && DISP_IN_RANGE (cfun->machine->frame_size + area_top-1))
{
/* Area is in range. */
offset = cfun->machine->frame_size;
*************** s390_emit_epilogue ()
*** 5710,5719 ****
offset = area_bottom < 0 ? -area_bottom : 0;
frame_off = GEN_INT (cfun->machine->frame_size - offset);
! if (!CONST_OK_FOR_LETTER_P (INTVAL (frame_off), 'K'))
! frame_off = force_const_mem (Pmode, frame_off);
! insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
}
/* Restore call saved fprs. */
--- 5833,5851 ----
offset = area_bottom < 0 ? -area_bottom : 0;
frame_off = GEN_INT (cfun->machine->frame_size - offset);
! if (DISP_IN_RANGE (INTVAL (frame_off)))
! {
! insn = gen_rtx_SET (VOIDmode, frame_pointer,
! gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
! insn = emit_insn (insn);
! }
! else
! {
! if (!CONST_OK_FOR_LETTER_P (INTVAL (frame_off), 'K'))
! frame_off = force_const_mem (Pmode, frame_off);
! insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
! }
}
/* Restore call saved fprs. */
*************** s390_output_mi_thunk (file, thunk, delta
*** 6649,6656 ****
if (TARGET_64BIT)
{
/* Setup literal pool pointer if required. */
! if (!CONST_OK_FOR_LETTER_P (delta, 'K')
! || !CONST_OK_FOR_LETTER_P (vcall_offset, 'K'))
{
op[5] = gen_label_rtx ();
output_asm_insn ("larl\t%4,%5", op);
--- 6781,6790 ----
if (TARGET_64BIT)
{
/* Setup literal pool pointer if required. */
! if ((!DISP_IN_RANGE (delta)
! && !CONST_OK_FOR_LETTER_P (delta, 'K'))
! || (!DISP_IN_RANGE (vcall_offset)
! && !CONST_OK_FOR_LETTER_P (vcall_offset, 'K')))
{
op[5] = gen_label_rtx ();
output_asm_insn ("larl\t%4,%5", op);
*************** s390_output_mi_thunk (file, thunk, delta
*** 6661,6666 ****
--- 6795,6802 ----
{
if (CONST_OK_FOR_LETTER_P (delta, 'J'))
output_asm_insn ("la\t%1,%2(%1)", op);
+ else if (DISP_IN_RANGE (delta))
+ output_asm_insn ("lay\t%1,%2(%1)", op);
else if (CONST_OK_FOR_LETTER_P (delta, 'K'))
output_asm_insn ("aghi\t%1,%2", op);
else
*************** s390_output_mi_thunk (file, thunk, delta
*** 6673,6679 ****
/* Perform vcall adjustment. */
if (vcall_offset)
{
! if (CONST_OK_FOR_LETTER_P (vcall_offset, 'J'))
{
output_asm_insn ("lg\t%4,0(%1)", op);
output_asm_insn ("ag\t%1,%3(%4)", op);
--- 6809,6815 ----
/* Perform vcall adjustment. */
if (vcall_offset)
{
! if (DISP_IN_RANGE (vcall_offset))
{
output_asm_insn ("lg\t%4,0(%1)", op);
output_asm_insn ("ag\t%1,%3(%4)", op);
*************** s390_output_mi_thunk (file, thunk, delta
*** 6720,6727 ****
{
/* Setup base pointer if required. */
if (!vcall_offset
! || !CONST_OK_FOR_LETTER_P (delta, 'K')
! || !CONST_OK_FOR_LETTER_P (vcall_offset, 'K'))
{
op[5] = gen_label_rtx ();
output_asm_insn ("basr\t%4,0", op);
--- 6856,6865 ----
{
/* Setup base pointer if required. */
if (!vcall_offset
! || (!DISP_IN_RANGE (delta)
! && !CONST_OK_FOR_LETTER_P (delta, 'K'))
! || (!DISP_IN_RANGE (delta)
! && !CONST_OK_FOR_LETTER_P (vcall_offset, 'K')))
{
op[5] = gen_label_rtx ();
output_asm_insn ("basr\t%4,0", op);
*************** s390_output_mi_thunk (file, thunk, delta
*** 6734,6739 ****
--- 6872,6879 ----
{
if (CONST_OK_FOR_LETTER_P (delta, 'J'))
output_asm_insn ("la\t%1,%2(%1)", op);
+ else if (DISP_IN_RANGE (delta))
+ output_asm_insn ("lay\t%1,%2(%1)", op);
else if (CONST_OK_FOR_LETTER_P (delta, 'K'))
output_asm_insn ("ahi\t%1,%2", op);
else
*************** s390_output_mi_thunk (file, thunk, delta
*** 6750,6755 ****
--- 6890,6900 ----
{
output_asm_insn ("lg\t%4,0(%1)", op);
output_asm_insn ("a\t%1,%3(%4)", op);
+ }
+ else if (DISP_IN_RANGE (vcall_offset))
+ {
+ output_asm_insn ("lg\t%4,0(%1)", op);
+ output_asm_insn ("ay\t%1,%3(%4)", op);
}
else if (CONST_OK_FOR_LETTER_P (vcall_offset, 'K'))
{
Index: gcc/config/s390/s390.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.h,v
retrieving revision 1.76
diff -c -p -r1.76 s390.h
*** gcc/config/s390/s390.h 30 Jun 2003 19:47:22 -0000 1.76
--- gcc/config/s390/s390.h 30 Jun 2003 22:02:44 -0000
*************** extern const enum reg_class regclass_map
*** 530,539 ****
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
#define EXTRA_CONSTRAINT(OP, C) \
! ((C) == 'Q' ? q_constraint (OP) : \
! (C) == 'S' ? larl_operand (OP, GET_MODE (OP)) : 0)
!
! #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'Q')
/* Stack layout and calling conventions. */
--- 530,540 ----
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
#define EXTRA_CONSTRAINT(OP, C) \
! s390_extra_constraint ((OP), (C))
! #define EXTRA_MEMORY_CONSTRAINT(C, STR) \
! ((C) == 'Q' || (C) == 'R' || (C) == 'S' || (C) == 'T')
! #define EXTRA_ADDRESS_CONSTRAINT(C, STR) \
! ((C) == 'U' || (C) == 'W')
/* Stack layout and calling conventions. */
Index: gcc/config/s390/s390.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.md,v
retrieving revision 1.58
diff -c -p -r1.58 s390.md
*** gcc/config/s390/s390.md 30 Jun 2003 22:01:00 -0000 1.58
--- gcc/config/s390/s390.md 30 Jun 2003 22:02:47 -0000
***************
*** 94,100 ****
;; Operand type. Used to default length attribute values
(define_attr "op_type"
! "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
(const_string "RX"))
;; Insn are devide in two classes:
--- 94,100 ----
;; Operand type. Used to default length attribute values
(define_attr "op_type"
! "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
(const_string "RX"))
;; Insn are devide in two classes:
***************
*** 115,121 ****
(eq_attr "op_type" "SSE") (const_string "agen")
(eq_attr "op_type" "RXE") (const_string "agen")
(eq_attr "op_type" "RSE") (const_string "agen")
! (eq_attr "op_type" "RIL") (const_string "agen")]
(const_string "reg")))
;; Generic pipeline function unit.
--- 115,124 ----
(eq_attr "op_type" "SSE") (const_string "agen")
(eq_attr "op_type" "RXE") (const_string "agen")
(eq_attr "op_type" "RSE") (const_string "agen")
! (eq_attr "op_type" "RIL") (const_string "agen")
! (eq_attr "op_type" "RXY") (const_string "agen")
! (eq_attr "op_type" "RSY") (const_string "agen")
! (eq_attr "op_type" "SIY") (const_string "agen")]
(const_string "reg")))
;; Generic pipeline function unit.
***************
*** 237,243 ****
(eq_attr "op_type" "SSE") (const_int 6)
(eq_attr "op_type" "RXE") (const_int 6)
(eq_attr "op_type" "RSE") (const_int 6)
! (eq_attr "op_type" "RIL") (const_int 6)]
(const_int 4)))
;; Define attributes for `asm' insns.
--- 240,249 ----
(eq_attr "op_type" "SSE") (const_int 6)
(eq_attr "op_type" "RXE") (const_int 6)
(eq_attr "op_type" "RSE") (const_int 6)
! (eq_attr "op_type" "RIL") (const_int 6)
! (eq_attr "op_type" "RXY") (const_int 6)
! (eq_attr "op_type" "RSY") (const_int 6)
! (eq_attr "op_type" "SIY") (const_int 6)]
(const_int 4)))
;; Define attributes for `asm' insns.
***************
*** 378,386 ****
(define_insn "*tmqi_ext"
[(set (reg 33)
! (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
! (match_operand:SI 1 "const_int_operand" "n")
! (match_operand:SI 2 "const_int_operand" "n"))
(const_int 0)))]
"s390_match_ccmode(insn, CCTmode)
&& INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
--- 384,392 ----
(define_insn "*tmqi_ext"
[(set (reg 33)
! (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,S")
! (match_operand:SI 1 "const_int_operand" "n,n")
! (match_operand:SI 2 "const_int_operand" "n,n"))
(const_int 0)))]
"s390_match_ccmode(insn, CCTmode)
&& INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
***************
*** 391,407 ****
int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
operands[2] = GEN_INT (block << shift);
! return \"tm\\t%0,%b2\";
}"
! [(set_attr "op_type" "SI")])
; Test-under-Mask instructions
(define_insn "*tmdi_mem"
[(set (reg 33)
! (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
! (match_operand:DI 1 "immediate_operand" "n"))
! (match_operand:DI 2 "immediate_operand" "n")))]
"TARGET_64BIT
&& s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], DImode, 0) >= 0"
--- 397,413 ----
int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
operands[2] = GEN_INT (block << shift);
! return which_alternative == 0 ? \"tm\\t%0,%b2\" : \"tmy\\t%0,%b2\";
}"
! [(set_attr "op_type" "SI,SIY")])
; Test-under-Mask instructions
(define_insn "*tmdi_mem"
[(set (reg 33)
! (compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S")
! (match_operand:DI 1 "immediate_operand" "n,n"))
! (match_operand:DI 2 "immediate_operand" "n,n")))]
"TARGET_64BIT
&& s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], DImode, 0) >= 0"
***************
*** 412,426 ****
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
! return \"tm\\t%0,%b1\";
}"
! [(set_attr "op_type" "SI")])
(define_insn "*tmsi_mem"
[(set (reg 33)
! (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
! (match_operand:SI 1 "immediate_operand" "n"))
! (match_operand:SI 2 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], SImode, 0) >= 0"
"*
--- 418,432 ----
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
! return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}"
! [(set_attr "op_type" "SI,SIY")])
(define_insn "*tmsi_mem"
[(set (reg 33)
! (compare (and:SI (match_operand:SI 0 "memory_operand" "Q,S")
! (match_operand:SI 1 "immediate_operand" "n,n"))
! (match_operand:SI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], SImode, 0) >= 0"
"*
***************
*** 430,444 ****
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
! return \"tm\\t%0,%b1\";
}"
[(set_attr "op_type" "SI")])
(define_insn "*tmhi_mem"
[(set (reg 33)
! (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
! (match_operand:SI 1 "immediate_operand" "n"))
! (match_operand:SI 2 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], HImode, 0) >= 0"
"*
--- 436,450 ----
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
! return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}"
[(set_attr "op_type" "SI")])
(define_insn "*tmhi_mem"
[(set (reg 33)
! (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q,S") 0)
! (match_operand:SI 1 "immediate_operand" "n,n"))
! (match_operand:SI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], HImode, 0) >= 0"
"*
***************
*** 448,465 ****
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
! return \"tm\\t%0,%b1\";
}"
[(set_attr "op_type" "SI")])
(define_insn "*tmqi_mem"
[(set (reg 33)
! (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
! (match_operand:SI 1 "immediate_operand" "n"))
! (match_operand:SI 2 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
! "tm\\t%0,%b1"
! [(set_attr "op_type" "SI")])
(define_insn "*tmdi_reg"
[(set (reg 33)
--- 454,473 ----
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
! return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}"
[(set_attr "op_type" "SI")])
(define_insn "*tmqi_mem"
[(set (reg 33)
! (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q,S") 0)
! (match_operand:SI 1 "immediate_operand" "n,n"))
! (match_operand:SI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
! "@
! tm\\t%0,%b1
! tmy\\t%0,%b1"
! [(set_attr "op_type" "SI,SIY")])
(define_insn "*tmdi_reg"
[(set (reg 33)
***************
*** 566,591 ****
(define_insn "*tstsi"
[(set (reg 33)
! (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
(match_operand:SI 1 "const0_operand" "")))
! (set (match_operand:SI 2 "register_operand" "=d,d")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\\t%2,%0
! icm\\t%2,15,%0"
! [(set_attr "op_type" "RR,RS")])
(define_insn "*tstsi_cconly"
[(set (reg 33)
! (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
(match_operand:SI 1 "const0_operand" "")))
! (clobber (match_scratch:SI 2 "=X,d"))]
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\\t%0,%0
! icm\\t%2,15,%0"
! [(set_attr "op_type" "RR,RS")])
(define_insn "*tstsi_cconly2"
[(set (reg 33)
--- 574,601 ----
(define_insn "*tstsi"
[(set (reg 33)
! (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
(match_operand:SI 1 "const0_operand" "")))
! (set (match_operand:SI 2 "register_operand" "=d,d,d")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\\t%2,%0
! icm\\t%2,15,%0
! icmy\\t%2,15,%0"
! [(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly"
[(set (reg 33)
! (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
(match_operand:SI 1 "const0_operand" "")))
! (clobber (match_scratch:SI 2 "=X,d,d"))]
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\\t%0,%0
! icm\\t%2,15,%0
! icmy\\t%2,15,%0"
! [(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly2"
[(set (reg 33)
***************
*** 597,682 ****
(define_insn "*tsthiCCT"
[(set (reg 33)
! (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d")
(match_operand:HI 1 "const0_operand" "")))
! (set (match_operand:HI 2 "register_operand" "=d,0")
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,3,%0
tml\\t%0,65535"
! [(set_attr "op_type" "RS,RI")])
(define_insn "*tsthiCCT_cconly"
[(set (reg 33)
! (compare (match_operand:HI 0 "nonimmediate_operand" "Q,d")
(match_operand:HI 1 "const0_operand" "")))
! (clobber (match_scratch:HI 2 "=d,X"))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,3,%0
tml\\t%0,65535"
! [(set_attr "op_type" "RS,RI")])
(define_insn "*tsthi"
[(set (reg 33)
! (compare (match_operand:HI 0 "s_operand" "Q")
(match_operand:HI 1 "const0_operand" "")))
! (set (match_operand:HI 2 "register_operand" "=d")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
! "icm\\t%2,3,%0"
! [(set_attr "op_type" "RS")])
(define_insn "*tsthi_cconly"
[(set (reg 33)
! (compare (match_operand:HI 0 "s_operand" "Q")
(match_operand:HI 1 "const0_operand" "")))
! (clobber (match_scratch:HI 2 "=d"))]
"s390_match_ccmode(insn, CCSmode)"
! "icm\\t%2,3,%0"
! [(set_attr "op_type" "RS")])
(define_insn "*tstqiCCT"
[(set (reg 33)
! (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
(match_operand:QI 1 "const0_operand" "")))
! (set (match_operand:QI 2 "register_operand" "=d,0")
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,1,%0
tml\\t%0,255"
! [(set_attr "op_type" "RS,RI")])
(define_insn "*tstqiCCT_cconly"
[(set (reg 33)
! (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
(match_operand:QI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCTmode)"
"@
cli\\t%0,0
tml\\t%0,255"
! [(set_attr "op_type" "SI,RI")])
(define_insn "*tstqi"
[(set (reg 33)
! (compare (match_operand:QI 0 "s_operand" "Q")
(match_operand:QI 1 "const0_operand" "")))
! (set (match_operand:QI 2 "register_operand" "=d")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
! "icm\\t%2,1,%0"
! [(set_attr "op_type" "RS")])
(define_insn "*tstqi_cconly"
[(set (reg 33)
! (compare (match_operand:QI 0 "s_operand" "Q")
(match_operand:QI 1 "const0_operand" "")))
! (clobber (match_scratch:QI 2 "=d"))]
"s390_match_ccmode(insn, CCSmode)"
! "icm\\t%2,1,%0"
! [(set_attr "op_type" "RS")])
; Compare (signed) instructions
--- 607,705 ----
(define_insn "*tsthiCCT"
[(set (reg 33)
! (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:HI 1 "const0_operand" "")))
! (set (match_operand:HI 2 "register_operand" "=d,d,0")
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,3,%0
+ icmy\\t%2,3,%0
tml\\t%0,65535"
! [(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tsthiCCT_cconly"
[(set (reg 33)
! (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
(match_operand:HI 1 "const0_operand" "")))
! (clobber (match_scratch:HI 2 "=d,d,X"))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,3,%0
+ icmy\\t%2,3,%0
tml\\t%0,65535"
! [(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tsthi"
[(set (reg 33)
! (compare (match_operand:HI 0 "s_operand" "Q,S")
(match_operand:HI 1 "const0_operand" "")))
! (set (match_operand:HI 2 "register_operand" "=d,d")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
! "@
! icm\\t%2,3,%0
! icmy\\t%2,3,%0"
! [(set_attr "op_type" "RS,RSY")])
(define_insn "*tsthi_cconly"
[(set (reg 33)
! (compare (match_operand:HI 0 "s_operand" "Q,S")
(match_operand:HI 1 "const0_operand" "")))
! (clobber (match_scratch:HI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
! "@
! icm\\t%2,3,%0
! icmy\\t%2,3,%0"
! [(set_attr "op_type" "RS,RSY")])
(define_insn "*tstqiCCT"
[(set (reg 33)
! (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:QI 1 "const0_operand" "")))
! (set (match_operand:QI 2 "register_operand" "=d,d,0")
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,1,%0
+ icmy\\t%2,1,%0
tml\\t%0,255"
! [(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tstqiCCT_cconly"
[(set (reg 33)
! (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:QI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCTmode)"
"@
cli\\t%0,0
+ cliy\\t%0,0
tml\\t%0,255"
! [(set_attr "op_type" "SI,SIY,RI")])
(define_insn "*tstqi"
[(set (reg 33)
! (compare (match_operand:QI 0 "s_operand" "Q,S")
(match_operand:QI 1 "const0_operand" "")))
! (set (match_operand:QI 2 "register_operand" "=d,d")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
! "@
! icm\\t%2,1,%0
! icmy\\t%2,1,%0"
! [(set_attr "op_type" "RS,RSY")])
(define_insn "*tstqi_cconly"
[(set (reg 33)
! (compare (match_operand:QI 0 "s_operand" "Q,S")
(match_operand:QI 1 "const0_operand" "")))
! (clobber (match_scratch:QI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
! "@
! icm\\t%2,1,%0
! icmy\\t%2,1,%0"
! [(set_attr "op_type" "RS,RSY")])
!
; Compare (signed) instructions
***************
*** 688,694 ****
"@
cgfr\\t%0,%1
cgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*cmpdi_ccs"
[(set (reg 33)
--- 711,717 ----
"@
cgfr\\t%0,%1
cgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccs"
[(set (reg 33)
***************
*** 699,724 ****
cgr\\t%0,%1
cghi\\t%0,%c1
cg\\t%0,%1"
! [(set_attr "op_type" "RRE,RI,RXE")])
(define_insn "*cmpsi_ccs_sign"
[(set (reg 33)
! (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
! (match_operand:SI 0 "register_operand" "d")))]
"s390_match_ccmode(insn, CCSRmode)"
! "ch\\t%0,%1"
! [(set_attr "op_type" "RX")])
(define_insn "*cmpsi_ccs"
[(set (reg 33)
! (compare (match_operand:SI 0 "register_operand" "d,d,d")
! (match_operand:SI 1 "general_operand" "d,K,m")))]
"s390_match_ccmode(insn, CCSmode)"
"@
cr\\t%0,%1
chi\\t%0,%c1
! c\\t%0,%1"
! [(set_attr "op_type" "RR,RI,RX")])
; Compare (unsigned) instructions
--- 722,750 ----
cgr\\t%0,%1
cghi\\t%0,%c1
cg\\t%0,%1"
! [(set_attr "op_type" "RRE,RI,RXY")])
(define_insn "*cmpsi_ccs_sign"
[(set (reg 33)
! (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
! (match_operand:SI 0 "register_operand" "d,d")))]
"s390_match_ccmode(insn, CCSRmode)"
! "@
! ch\\t%0,%1
! chy\\t%0,%1"
! [(set_attr "op_type" "RX,RXY")])
(define_insn "*cmpsi_ccs"
[(set (reg 33)
! (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
! (match_operand:SI 1 "general_operand" "d,K,R,T")))]
"s390_match_ccmode(insn, CCSmode)"
"@
cr\\t%0,%1
chi\\t%0,%c1
! c\\t%0,%1
! cy\\t%0,%1"
! [(set_attr "op_type" "RR,RI,RX,RXY")])
; Compare (unsigned) instructions
***************
*** 731,737 ****
"@
clgfr\\t%0,%1
clgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*cmpdi_ccu"
[(set (reg 33)
--- 757,763 ----
"@
clgfr\\t%0,%1
clgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccu"
[(set (reg 33)
***************
*** 741,781 ****
"@
clgr\\t%0,%1
clg\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*cmpsi_ccu"
[(set (reg 33)
! (compare (match_operand:SI 0 "register_operand" "d,d")
! (match_operand:SI 1 "general_operand" "d,m")))]
"s390_match_ccmode(insn, CCUmode)"
"@
clr\\t%0,%1
! cl\\t%0,%1"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*cmphi_ccu"
[(set (reg 33)
! (compare (match_operand:HI 0 "register_operand" "d")
! (match_operand:HI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
! "clm\\t%0,3,%1"
! [(set_attr "op_type" "RS")])
(define_insn "*cmpqi_ccu"
[(set (reg 33)
! (compare (match_operand:QI 0 "register_operand" "d")
! (match_operand:QI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
! "clm\\t%0,1,%1"
! [(set_attr "op_type" "RS")])
(define_insn "*cli"
[(set (reg 33)
! (compare (match_operand:QI 0 "memory_operand" "Q")
! (match_operand:QI 1 "immediate_operand" "n")))]
"s390_match_ccmode (insn, CCUmode)"
! "cli\\t%0,%b1"
! [(set_attr "op_type" "SI")])
(define_insn "*cmpdi_ccu_mem"
[(set (reg 33)
--- 767,814 ----
"@
clgr\\t%0,%1
clg\\t%0,%1"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpsi_ccu"
[(set (reg 33)
! (compare (match_operand:SI 0 "register_operand" "d,d,d")
! (match_operand:SI 1 "general_operand" "d,R,T")))]
"s390_match_ccmode(insn, CCUmode)"
"@
clr\\t%0,%1
! cl\\t%0,%1
! cly\\t%0,%1"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*cmphi_ccu"
[(set (reg 33)
! (compare (match_operand:HI 0 "register_operand" "d,d")
! (match_operand:HI 1 "s_imm_operand" "Q,S")))]
"s390_match_ccmode(insn, CCUmode)"
! "@
! clm\\t%0,3,%1
! clmy\\t%0,3,%1"
! [(set_attr "op_type" "RS,RSY")])
(define_insn "*cmpqi_ccu"
[(set (reg 33)
! (compare (match_operand:QI 0 "register_operand" "d,d")
! (match_operand:QI 1 "s_imm_operand" "Q,S")))]
"s390_match_ccmode(insn, CCUmode)"
! "@
! clm\\t%0,1,%1
! clmy\\t%0,1,%1"
! [(set_attr "op_type" "RS,RSY")])
(define_insn "*cli"
[(set (reg 33)
! (compare (match_operand:QI 0 "memory_operand" "Q,S")
! (match_operand:QI 1 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, CCUmode)"
! "@
! cli\\t%0,%b1
! cliy\\t%0,%b1"
! [(set_attr "op_type" "SI,SIY")])
(define_insn "*cmpdi_ccu_mem"
[(set (reg 33)
***************
*** 833,839 ****
(define_insn "*cmpdf_ccs"
[(set (reg 33)
(compare (match_operand:DF 0 "register_operand" "f,f")
! (match_operand:DF 1 "general_operand" "f,m")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
cdbr\\t%0,%1
--- 866,872 ----
(define_insn "*cmpdf_ccs"
[(set (reg 33)
(compare (match_operand:DF 0 "register_operand" "f,f")
! (match_operand:DF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
cdbr\\t%0,%1
***************
*** 844,850 ****
(define_insn "*cmpdf_ccs_ibm"
[(set (reg 33)
(compare (match_operand:DF 0 "register_operand" "f,f")
! (match_operand:DF 1 "general_operand" "f,m")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
cdr\\t%0,%1
--- 877,883 ----
(define_insn "*cmpdf_ccs_ibm"
[(set (reg 33)
(compare (match_operand:DF 0 "register_operand" "f,f")
! (match_operand:DF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
cdr\\t%0,%1
***************
*** 876,882 ****
(define_insn "*cmpsf_ccs"
[(set (reg 33)
(compare (match_operand:SF 0 "register_operand" "f,f")
! (match_operand:SF 1 "general_operand" "f,m")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
cebr\\t%0,%1
--- 909,915 ----
(define_insn "*cmpsf_ccs"
[(set (reg 33)
(compare (match_operand:SF 0 "register_operand" "f,f")
! (match_operand:SF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
cebr\\t%0,%1
***************
*** 887,893 ****
(define_insn "*cmpsf_ccs"
[(set (reg 33)
(compare (match_operand:SF 0 "register_operand" "f,f")
! (match_operand:SF 1 "general_operand" "f,m")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
cer\\t%0,%1
--- 920,926 ----
(define_insn "*cmpsf_ccs"
[(set (reg 33)
(compare (match_operand:SF 0 "register_operand" "f,f")
! (match_operand:SF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
cer\\t%0,%1
***************
*** 905,912 ****
;
(define_insn "movti"
! [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,o,Q")
! (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
"TARGET_64BIT"
"@
lmg\\t%0,%N0,%1
--- 938,945 ----
;
(define_insn "movti"
! [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
! (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
"TARGET_64BIT"
"@
lmg\\t%0,%N0,%1
***************
*** 914,920 ****
#
#
mvc\\t%O0(16,%R0),%1"
! [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
(set_attr "type" "lm,stm,*,*,cs")])
(define_split
--- 947,953 ----
#
#
mvc\\t%O0(16,%R0),%1"
! [(set_attr "op_type" "RSY,RSY,NN,NN,SS")
(set_attr "type" "lm,stm,*,*,cs")])
(define_split
***************
*** 1023,1028 ****
--- 1056,1072 ----
}"
[(set_attr "op_type" "RI")])
+ (define_insn "*movdi_lay"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (match_operand:DI 1 "address_operand" "p"))]
+ "TARGET_64BIT
+ && TARGET_LONG_DISPLACEMENT
+ && GET_CODE (operands[1]) == CONST_INT
+ && !FP_REG_P (operands[0])"
+ "lay\\t%0,%a1"
+ [(set_attr "op_type" "RXY")
+ (set_attr "type" "la")])
+
(define_insn "*movdi_larl"
[(set (match_operand:DI 0 "register_operand" "=d")
(match_operand:DI 1 "larl_operand" "X"))]
***************
*** 1033,1040 ****
(set_attr "type" "larl")])
(define_insn "*movdi_64"
! [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,?Q")
! (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,?Q"))]
"TARGET_64BIT"
"@
lgr\\t%0,%1
--- 1077,1084 ----
(set_attr "type" "larl")])
(define_insn "*movdi_64"
! [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!*f,!R,!T,?Q")
! (match_operand:DI 1 "general_operand" "d,m,d,*f,R,T,*f,*f,?Q"))]
"TARGET_64BIT"
"@
lgr\\t%0,%1
***************
*** 1042,1055 ****
stg\\t%1,%0
ldr\\t%0,%1
ld\\t%0,%1
std\\t%1,%0
mvc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS")
! (set_attr "type" "lr,load,store,floadd,floadd,fstored,cs")])
(define_insn "*movdi_31"
! [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!m,Q")
! (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
"!TARGET_64BIT"
"@
lm\\t%0,%N0,%1
--- 1086,1101 ----
stg\\t%1,%0
ldr\\t%0,%1
ld\\t%0,%1
+ ldy\\t%0,%1
std\\t%1,%0
+ stdy\\t%1,%0
mvc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS")
! (set_attr "type" "lr,load,store,floadd,floadd,floadd,fstored,fstored,cs")])
(define_insn "*movdi_31"
! [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
! (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
"!TARGET_64BIT"
"@
lm\\t%0,%N0,%1
***************
*** 1058,1067 ****
#
ldr\\t%0,%1
ld\\t%0,%1
std\\t%1,%0
mvc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
! (set_attr "type" "lm,stm,*,*,floadd,floadd,fstored,cs")])
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
--- 1104,1115 ----
#
ldr\\t%0,%1
ld\\t%0,%1
+ ldy\\t%0,%1
std\\t%1,%0
+ stdy\\t%1,%0
mvc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS")
! (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")])
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
***************
*** 1192,1211 ****
}"
[(set_attr "op_type" "RI")])
(define_insn "*movsi"
! [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,?Q")
! (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,?Q"))]
""
"@
lr\\t%0,%1
l\\t%0,%1
st\\t%1,%0
ler\\t%0,%1
le\\t%0,%1
ste\\t%1,%0
mvc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
! (set_attr "type" "lr,load,store,floads,floads,fstores,cs")])
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
--- 1240,1273 ----
}"
[(set_attr "op_type" "RI")])
+ (define_insn "*movsi_lay"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (match_operand:SI 1 "address_operand" "p"))]
+ "TARGET_LONG_DISPLACEMENT
+ && GET_CODE (operands[1]) == CONST_INT
+ && !FP_REG_P (operands[0])"
+ "lay\\t%0,%a1"
+ [(set_attr "op_type" "RXY")
+ (set_attr "type" "la")])
+
(define_insn "*movsi"
! [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q")
! (match_operand:SI 1 "general_operand" "d,R,T,d,d,*f,R,T,*f,*f,?Q"))]
""
"@
lr\\t%0,%1
l\\t%0,%1
+ ly\\t%0,%1
st\\t%1,%0
+ sty\\t%1,%0
ler\\t%0,%1
le\\t%0,%1
+ ley\\t%0,%1
ste\\t%1,%0
+ stey\\t%1,%0
mvc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
! (set_attr "type" "lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")])
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
***************
*** 1223,1239 ****
;
(define_insn "movhi"
! [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,?Q")
! (match_operand:HI 1 "general_operand" "d,n,m,d,?Q"))]
""
"@
lr\\t%0,%1
lhi\\t%0,%h1
lh\\t%0,%1
sth\\t%1,%0
mvc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "RR,RI,RX,RX,SS")
! (set_attr "type" "lr,*,*,store,cs")])
(define_peephole2
[(set (match_operand:HI 0 "register_operand" "")
--- 1285,1303 ----
;
(define_insn "movhi"
! [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
! (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
""
"@
lr\\t%0,%1
lhi\\t%0,%h1
lh\\t%0,%1
+ lhy\\t%0,%1
sth\\t%1,%0
+ sthy\\t%1,%0
mvc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
! (set_attr "type" "lr,*,*,*,store,store,cs")])
(define_peephole2
[(set (match_operand:HI 0 "register_operand" "")
***************
*** 1250,1281 ****
;
(define_insn "movqi_64"
! [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,?Q")
! (match_operand:QI 1 "general_operand" "d,n,m,d,n,?Q"))]
"TARGET_64BIT"
"@
lr\\t%0,%1
lhi\\t%0,%b1
llgc\\t%0,%1
stc\\t%1,%0
mvi\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
! (set_attr "type" "lr,*,*,store,store,cs")])
(define_insn "movqi"
! [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,?Q")
! (match_operand:QI 1 "general_operand" "d,n,m,d,n,?Q"))]
""
"@
lr\\t%0,%1
lhi\\t%0,%b1
ic\\t%0,%1
stc\\t%1,%0
mvi\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
! (set_attr "type" "lr,*,*,store,store,cs")])
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
--- 1314,1350 ----
;
(define_insn "movqi_64"
! [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,R,T,Q,S,?Q")
! (match_operand:QI 1 "general_operand" "d,n,m,d,d,n,n,?Q"))]
"TARGET_64BIT"
"@
lr\\t%0,%1
lhi\\t%0,%b1
llgc\\t%0,%1
stc\\t%1,%0
+ stcy\\t%1,%0
mvi\\t%0,%b1
+ mviy\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "RR,RI,RXY,RX,RXY,SI,SIY,SS")
! (set_attr "type" "lr,*,*,store,store,store,store,cs")])
(define_insn "movqi"
! [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
! (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
""
"@
lr\\t%0,%1
lhi\\t%0,%b1
ic\\t%0,%1
+ icy\\t%0,%1
stc\\t%1,%0
+ stcy\\t%1,%0
mvi\\t%0,%b1
+ mviy\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
! (set_attr "type" "lr,*,*,*,store,store,store,store,cs")])
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
***************
*** 1292,1330 ****
;
(define_insn "*movstrictqi"
! [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
! (match_operand:QI 1 "memory_operand" "m"))]
""
! "ic\\t%0,%1"
! [(set_attr "op_type" "RX")])
;
; movstricthi instruction pattern(s).
;
(define_insn "*movstricthi"
! [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
! (match_operand:HI 1 "s_imm_operand" "Q"))
(clobber (reg:CC 33))]
""
! "icm\\t%0,3,%1"
! [(set_attr "op_type" "RS")])
!
;
; movstrictsi instruction pattern(s).
;
(define_insn "movstrictsi"
! [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
! (match_operand:SI 1 "general_operand" "d,m"))]
"TARGET_64BIT"
"@
lr\\t%0,%1
! l\\t%0,%1"
! [(set_attr "op_type" "RR,RS")
! (set_attr "type" "lr,load")])
!
;
; movdf instruction pattern(s).
--- 1361,1402 ----
;
(define_insn "*movstrictqi"
! [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
! (match_operand:QI 1 "memory_operand" "R,T"))]
""
! "@
! ic\\t%0,%1
! icy\\t%0,%1"
! [(set_attr "op_type" "RX,RXY")])
;
; movstricthi instruction pattern(s).
;
(define_insn "*movstricthi"
! [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
! (match_operand:HI 1 "s_imm_operand" "Q,S"))
(clobber (reg:CC 33))]
""
! "@
! icm\\t%0,3,%1
! icmy\\t%0,3,%1"
! [(set_attr "op_type" "RS,RSY")])
;
; movstrictsi instruction pattern(s).
;
(define_insn "movstrictsi"
! [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d"))
! (match_operand:SI 1 "general_operand" "d,R,T"))]
"TARGET_64BIT"
"@
lr\\t%0,%1
! l\\t%0,%1
! ly\\t%0,%1"
! [(set_attr "op_type" "RR,RX,RXY")
! (set_attr "type" "lr,load,load")])
;
; movdf instruction pattern(s).
***************
*** 1344,1378 ****
}")
(define_insn "*movdf_64"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,?Q")
! (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,?Q"))]
"TARGET_64BIT"
"@
ldr\\t%0,%1
ld\\t%0,%1
std\\t%1,%0
lgr\\t%0,%1
lg\\t%0,%1
stg\\t%1,%0
mvc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS")
! (set_attr "type" "floadd,floadd,fstored,lr,load,store,cs")])
(define_insn "*movdf_31"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,o,Q")
! (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
"!TARGET_64BIT"
"@
ldr\\t%0,%1
ld\\t%0,%1
std\\t%1,%0
lm\\t%0,%N0,%1
stm\\t%1,%N1,%0
#
#
mvc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
! (set_attr "type" "floadd,floadd,fstored,lm,stm,*,*,cs")])
(define_split
[(set (match_operand:DF 0 "nonimmediate_operand" "")
--- 1416,1454 ----
}")
(define_insn "*movdf_64"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
! (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
"TARGET_64BIT"
"@
ldr\\t%0,%1
ld\\t%0,%1
+ ldy\\t%0,%1
std\\t%1,%0
+ stdy\\t%1,%0
lgr\\t%0,%1
lg\\t%0,%1
stg\\t%1,%0
mvc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
! (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")])
(define_insn "*movdf_31"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
! (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
"!TARGET_64BIT"
"@
ldr\\t%0,%1
ld\\t%0,%1
+ ldy\\t%0,%1
std\\t%1,%0
+ stdy\\t%1,%0
lm\\t%0,%N0,%1
stm\\t%1,%N1,%0
#
#
mvc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS")
! (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")])
(define_split
[(set (match_operand:DF 0 "nonimmediate_operand" "")
***************
*** 1445,1463 ****
}")
(define_insn "*movsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,?Q")
! (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,?Q"))]
""
"@
ler\\t%0,%1
le\\t%0,%1
ste\\t%1,%0
lr\\t%0,%1
l\\t%0,%1
st\\t%1,%0
mvc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
! (set_attr "type" "floads,floads,fstores,lr,load,store,cs")])
;
; load_multiple pattern(s).
--- 1521,1543 ----
}")
(define_insn "*movsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
! (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
""
"@
ler\\t%0,%1
le\\t%0,%1
+ ley\\t%0,%1
ste\\t%1,%0
+ stey\\t%1,%0
lr\\t%0,%1
l\\t%0,%1
+ ly\\t%0,%1
st\\t%1,%0
+ sty\\t%1,%0
mvc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
! (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")])
;
; load_multiple pattern(s).
***************
*** 1526,1562 ****
(define_insn "*load_multiple_di"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r")
! (match_operand:DI 2 "s_operand" "Q"))])]
""
"*
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"lg\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
! return \"lmg\\t%1,%0,%2\";
}"
! [(set_attr "op_type" "RXE")
(set_attr "type" "lm")])
(define_insn "*load_multiple_si"
[(match_parallel 0 "load_multiple_operation"
! [(set (match_operand:SI 1 "register_operand" "=r")
! (match_operand:SI 2 "s_operand" "Q"))])]
""
"*
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"l\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
! return \"lm\\t%1,%0,%2\";
}"
! [(set_attr "op_type" "RXE")
(set_attr "type" "lm")])
;
--- 1606,1634 ----
(define_insn "*load_multiple_di"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r")
! (match_operand:DI 2 "s_operand" "QS"))])]
""
"*
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
! return \"lmg\\t%1,%0,%2\";
}"
! [(set_attr "op_type" "RSY")
(set_attr "type" "lm")])
(define_insn "*load_multiple_si"
[(match_parallel 0 "load_multiple_operation"
! [(set (match_operand:SI 1 "register_operand" "=r,r")
! (match_operand:SI 2 "s_operand" "Q,S"))])]
""
"*
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
! return which_alternative == 0 ? \"lm\\t%1,%0,%2\" : \"lmy\\t%1,%0,%2\";
}"
! [(set_attr "op_type" "RS,RSY")
(set_attr "type" "lm")])
;
***************
*** 1627,1665 ****
(define_insn "*store_multiple_di"
[(match_parallel 0 "store_multiple_operation"
! [(set (match_operand:DI 1 "s_operand" "=Q")
(match_operand:DI 2 "register_operand" "r"))])]
""
"*
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"stg\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
! return \"stmg\\t%2,%0,%1\";
}"
! [(set_attr "op_type" "RXE")
(set_attr "type" "stm")])
(define_insn "*store_multiple_si"
[(match_parallel 0 "store_multiple_operation"
! [(set (match_operand:SI 1 "s_operand" "=Q")
! (match_operand:SI 2 "register_operand" "r"))])]
""
"*
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"st\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
! return \"stm\\t%2,%0,%1\";
}"
! [(set_attr "op_type" "RXE")
(set_attr "type" "stm")])
;;
--- 1699,1729 ----
(define_insn "*store_multiple_di"
[(match_parallel 0 "store_multiple_operation"
! [(set (match_operand:DI 1 "s_operand" "=QS")
(match_operand:DI 2 "register_operand" "r"))])]
""
"*
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
! return \"stmg\\t%2,%0,%1\";
}"
! [(set_attr "op_type" "RSY")
(set_attr "type" "stm")])
(define_insn "*store_multiple_si"
[(match_parallel 0 "store_multiple_operation"
! [(set (match_operand:SI 1 "s_operand" "=Q,S")
! (match_operand:SI 2 "register_operand" "r,r"))])]
""
"*
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
! return which_alternative == 0 ? \"stm\\t%2,%0,%1\" : \"stmy\\t%2,%0,%1\";
}"
! [(set_attr "op_type" "RS,RSY")
(set_attr "type" "stm")])
;;
***************
*** 2043,2078 ****
;;
(define_insn "*sethighqisi"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
(clobber (reg:CC 33))]
""
! "icm\\t%0,8,%1"
! [(set_attr "op_type" "RS")])
(define_insn "*sethighhisi"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
(clobber (reg:CC 33))]
""
! "icm\\t%0,12,%1"
! [(set_attr "op_type" "RS")])
(define_insn "*sethighqidi_64"
[(set (match_operand:DI 0 "register_operand" "=d")
! (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
(clobber (reg:CC 33))]
"TARGET_64BIT"
"icmh\\t%0,8,%1"
! [(set_attr "op_type" "RSE")])
(define_insn "*sethighqidi_31"
! [(set (match_operand:DI 0 "register_operand" "=d")
! (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
(clobber (reg:CC 33))]
"!TARGET_64BIT"
! "icm\\t%0,8,%1"
! [(set_attr "op_type" "RS")])
(define_insn_and_split "*extractqi"
[(set (match_operand:SI 0 "register_operand" "=d")
--- 2107,2148 ----
;;
(define_insn "*sethighqisi"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] 10))
(clobber (reg:CC 33))]
""
! "@
! icm\\t%0,8,%1
! icmy\\t%0,8,%1"
! [(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighhisi"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] 10))
(clobber (reg:CC 33))]
""
! "@
! icm\\t%0,12,%1
! icmy\\t%0,12,%1"
! [(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighqidi_64"
[(set (match_operand:DI 0 "register_operand" "=d")
! (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] 10))
(clobber (reg:CC 33))]
"TARGET_64BIT"
"icmh\\t%0,8,%1"
! [(set_attr "op_type" "RSY")])
(define_insn "*sethighqidi_31"
! [(set (match_operand:DI 0 "register_operand" "=d,d")
! (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] 10))
(clobber (reg:CC 33))]
"!TARGET_64BIT"
! "@
! icm\\t%0,8,%1
! icmy\\t%0,8,%1"
! [(set_attr "op_type" "RS,RSY")])
(define_insn_and_split "*extractqi"
[(set (match_operand:SI 0 "register_operand" "=d")
***************
*** 2144,2150 ****
"@
lgfr\\t%0,%1
lgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")])
;
; extendhidi2 instruction pattern(s).
--- 2214,2220 ----
"@
lgfr\\t%0,%1
lgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXY")])
;
; extendhidi2 instruction pattern(s).
***************
*** 2178,2184 ****
(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"lgh\\t%0,%1"
! [(set_attr "op_type" "RXE")])
;
; extendqidi2 instruction pattern(s).
--- 2248,2254 ----
(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"lgh\\t%0,%1"
! [(set_attr "op_type" "RXY")])
;
; extendqidi2 instruction pattern(s).
***************
*** 2207,2216 ****
}
")
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
! "TARGET_64BIT && !reload_completed"
[(parallel
[(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
(clobber (reg:CC 33))])
--- 2277,2293 ----
}
")
+ (define_insn "*extendqidi2"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
+ "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
+ "lgb\\t%0,%1"
+ [(set_attr "op_type" "RXY")])
+
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
! "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT && !reload_completed"
[(parallel
[(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
(clobber (reg:CC 33))])
***************
*** 2237,2247 ****
")
(define_insn "*extendhisi2"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
""
! "lh\\t%0,%1"
! [(set_attr "op_type" "RX")])
;
; extendqisi2 instruction pattern(s).
--- 2314,2326 ----
")
(define_insn "*extendhisi2"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
""
! "@
! lh\\t%0,%1
! lhy\\t%0,%1"
! [(set_attr "op_type" "RX,RXY")])
;
; extendqisi2 instruction pattern(s).
***************
*** 2260,2269 ****
}
")
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
! "!reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
(clobber (reg:CC 33))])
--- 2339,2355 ----
}
")
+ (define_insn "*extendqisi2"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
+ "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
+ "lb\\t%0,%1"
+ [(set_attr "op_type" "RXY")])
+
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
! "(!TARGET_64BIT || !TARGET_LONG_DISPLACEMENT) && !reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
(clobber (reg:CC 33))])
***************
*** 2304,2310 ****
"@
llgfr\\t%0,%1
llgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")])
;
; zero_extendhidi2 instruction pattern(s).
--- 2390,2396 ----
"@
llgfr\\t%0,%1
llgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXY")])
;
; zero_extendhidi2 instruction pattern(s).
***************
*** 2338,2344 ****
(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
! [(set_attr "op_type" "RXE")])
;
; zero_extendqidi2 instruction pattern(s)
--- 2424,2430 ----
(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
! [(set_attr "op_type" "RXY")])
;
; zero_extendqidi2 instruction pattern(s)
***************
*** 2372,2378 ****
(zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
! [(set_attr "op_type" "RXE")])
;
; zero_extendhisi2 instruction pattern(s).
--- 2458,2464 ----
(zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
! [(set_attr "op_type" "RXY")])
;
; zero_extendhisi2 instruction pattern(s).
***************
*** 2395,2405 ****
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
! [(set_attr "op_type" "RXE")])
(define_insn_and_split "*zero_extendhisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
! (zero_extend:SI (match_operand:HI 1 "memory_operand" "Q")))
(clobber (reg:CC 33))]
"!TARGET_64BIT"
"#"
--- 2481,2491 ----
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
! [(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendhisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
! (zero_extend:SI (match_operand:HI 1 "memory_operand" "QS")))
(clobber (reg:CC 33))]
"!TARGET_64BIT"
"#"
***************
*** 2432,2438 ****
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
! [(set_attr "op_type" "RXE")])
(define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
--- 2518,2524 ----
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
! [(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
***************
*** 2466,2472 ****
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
! [(set_attr "op_type" "RXE")])
(define_insn_and_split "*zero_extendqihi2_31"
[(set (match_operand:HI 0 "register_operand" "=&d")
--- 2552,2558 ----
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
! [(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendqihi2_31"
[(set (match_operand:HI 0 "register_operand" "=&d")
***************
*** 2866,2872 ****
(define_insn "truncdfsf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
! (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
lrer\\t%0,%1
--- 2952,2958 ----
(define_insn "truncdfsf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
! (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
lrer\\t%0,%1
***************
*** 2893,2899 ****
(define_insn "extendsfdf2_ieee"
[(set (match_operand:DF 0 "register_operand" "=f,f")
! (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
ldebr\\t%0,%1
--- 2979,2985 ----
(define_insn "extendsfdf2_ieee"
[(set (match_operand:DF 0 "register_operand" "=f,f")
! (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
ldebr\\t%0,%1
***************
*** 2903,2909 ****
(define_insn "extendsfdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
! (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
--- 2989,2995 ----
(define_insn "extendsfdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
! (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
***************
*** 2939,2945 ****
"@
agfr\\t%0,%2
agf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_zero_cc"
[(set (reg 33)
--- 3025,3031 ----
"@
agfr\\t%0,%2
agf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cc"
[(set (reg 33)
***************
*** 2952,2958 ****
"@
algfr\\t%0,%2
algf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_zero_cconly"
[(set (reg 33)
--- 3038,3044 ----
"@
algfr\\t%0,%2
algf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cconly"
[(set (reg 33)
***************
*** 2964,2970 ****
"@
algfr\\t%0,%2
algf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 3050,3056 ----
"@
algfr\\t%0,%2
algf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 2975,2981 ****
"@
algfr\\t%0,%2
algf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_imm_cc"
[(set (reg 33)
--- 3061,3067 ----
"@
algfr\\t%0,%2
algf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_imm_cc"
[(set (reg 33)
***************
*** 3001,3007 ****
"@
algr\\t%0,%2
alg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_cconly"
[(set (reg 33)
--- 3087,3093 ----
"@
algr\\t%0,%2
alg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly"
[(set (reg 33)
***************
*** 3013,3019 ****
"@
algr\\t%0,%2
alg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_cconly2"
[(set (reg 33)
--- 3099,3105 ----
"@
algr\\t%0,%2
alg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly2"
[(set (reg 33)
***************
*** 3024,3030 ****
"@
algr\\t%0,%2
alg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
--- 3110,3116 ----
"@
algr\\t%0,%2
alg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
***************
*** 3036,3042 ****
agr\\t%0,%2
aghi\\t%0,%h2
ag\\t%0,%2"
! [(set_attr "op_type" "RRE,RI,RXE")])
(define_insn_and_split "*adddi3_31"
[(set (match_operand:DI 0 "register_operand" "=&d")
--- 3122,3128 ----
agr\\t%0,%2
aghi\\t%0,%h2
ag\\t%0,%2"
! [(set_attr "op_type" "RRE,RI,RXY")])
(define_insn_and_split "*adddi3_31"
[(set (match_operand:DI 0 "register_operand" "=&d")
***************
*** 3081,3091 ****
"")
(define_insn "*la_64"
! [(set (match_operand:DI 0 "register_operand" "=d")
! (match_operand:QI 1 "address_operand" "p"))]
"TARGET_64BIT"
! "la\\t%0,%a1"
! [(set_attr "op_type" "RX")
(set_attr "type" "la")])
(define_peephole2
--- 3167,3179 ----
"")
(define_insn "*la_64"
! [(set (match_operand:DI 0 "register_operand" "=d,d")
! (match_operand:QI 1 "address_operand" "U,W"))]
"TARGET_64BIT"
! "@
! la\\t%0,%a1
! lay\\t%0,%a1"
! [(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")])
(define_peephole2
***************
*** 3144,3269 ****
(define_insn "*addsi3_carry1_cc"
[(set (reg 33)
! (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(match_dup 1)))
! (set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
! al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_carry1_cconly"
[(set (reg 33)
! (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(match_dup 1)))
! (clobber (match_scratch:SI 0 "=d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
! al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_carry2_cc"
[(set (reg 33)
! (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(match_dup 2)))
! (set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
! al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_carry2_cconly"
[(set (reg 33)
! (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(match_dup 2)))
! (clobber (match_scratch:SI 0 "=d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
! al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_cc"
[(set (reg 33)
! (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
alr\\t%0,%2
! al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_cconly"
[(set (reg 33)
! (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d"))]
"s390_match_ccmode (insn, CCLmode)"
"@
alr\\t%0,%2
! al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_cconly2"
[(set (reg 33)
! (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
! (clobber (match_scratch:SI 0 "=d,d"))]
"s390_match_ccmode(insn, CCLmode)"
"@
alr\\t%0,%2
! al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_sign"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (plus:SI (match_operand:SI 1 "register_operand" "0")
! (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
(clobber (reg:CC 33))]
""
! "ah\\t%0,%2"
! [(set_attr "op_type" "RX")])
(define_insn "*addsi3_sub"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (plus:SI (match_operand:SI 1 "register_operand" "0")
! (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
(clobber (reg:CC 33))]
""
! "ah\\t%0,%2"
! [(set_attr "op_type" "RX")])
(define_insn "addsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d,d")
! (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,K,m")))
(clobber (reg:CC 33))]
""
"@
ar\\t%0,%2
ahi\\t%0,%h2
! a\\t%0,%2"
! [(set_attr "op_type" "RR,RI,RX")])
(define_insn "*la_31"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (match_operand:QI 1 "address_operand" "p"))]
"!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
! "la\\t%0,%a1"
! [(set_attr "op_type" "RX")
(set_attr "type" "la")])
(define_peephole2
--- 3232,3371 ----
(define_insn "*addsi3_carry1_cc"
[(set (reg 33)
! (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
! (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
! al\\t%0,%2
! aly\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry1_cconly"
[(set (reg 33)
! (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
! (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
! al\\t%0,%2
! aly\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cc"
[(set (reg 33)
! (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2)))
! (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
! al\\t%0,%2
! aly\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cconly"
[(set (reg 33)
! (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2)))
! (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
! al\\t%0,%2
! aly\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cc"
[(set (reg 33)
! (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
alr\\t%0,%2
! al\\t%0,%2
! aly\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly"
[(set (reg 33)
! (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCLmode)"
"@
alr\\t%0,%2
! al\\t%0,%2
! aly\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly2"
[(set (reg 33)
! (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
! (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCLmode)"
"@
alr\\t%0,%2
! al\\t%0,%2
! aly\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_sign"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (plus:SI (match_operand:SI 1 "register_operand" "0,0")
! (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
(clobber (reg:CC 33))]
""
! "@
! ah\\t%0,%2
! ahy\\t%0,%2"
! [(set_attr "op_type" "RX,RXY")])
(define_insn "*addsi3_sub"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (plus:SI (match_operand:SI 1 "register_operand" "0,0")
! (subreg:SI (match_operand:HI 2 "memory_operand" "R,T") 0)))
(clobber (reg:CC 33))]
""
! "@
! ah\\t%0,%2
! ahy\\t%0,%2"
! [(set_attr "op_type" "RX,RXY")])
(define_insn "addsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
! (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
! (match_operand:SI 2 "general_operand" "d,K,R,T")))
(clobber (reg:CC 33))]
""
"@
ar\\t%0,%2
ahi\\t%0,%h2
! a\\t%0,%2
! ay\\t%0,%2"
! [(set_attr "op_type" "RR,RI,RX,RXY")])
(define_insn "*la_31"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (match_operand:QI 1 "address_operand" "U,W"))]
"!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
! "@
! la\\t%0,%a1
! lay\\t%0,%a1"
! [(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")])
(define_peephole2
***************
*** 3293,3304 ****
"")
(define_insn "*la_31_and"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (and:SI (match_operand:QI 1 "address_operand" "p")
(const_int 2147483647)))]
"!TARGET_64BIT"
! "la\\t%0,%a1"
! [(set_attr "op_type" "RX")
(set_attr "type" "la")])
(define_insn_and_split "*la_31_and_cc"
--- 3395,3408 ----
"")
(define_insn "*la_31_and"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (and:SI (match_operand:QI 1 "address_operand" "U,W")
(const_int 2147483647)))]
"!TARGET_64BIT"
! "@
! la\\t%0,%a1
! lay\\t%0,%a1"
! [(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")])
(define_insn_and_split "*la_31_and_cc"
***************
*** 3316,3326 ****
(set_attr "type" "la")])
(define_insn "force_la_31"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (match_operand:QI 1 "address_operand" "p"))
(use (const_int 0))]
"!TARGET_64BIT"
! "la\\t%0,%a1"
[(set_attr "op_type" "RX")
(set_attr "type" "la")])
--- 3420,3432 ----
(set_attr "type" "la")])
(define_insn "force_la_31"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (match_operand:QI 1 "address_operand" "U,W"))
(use (const_int 0))]
"!TARGET_64BIT"
! "@
! la\\t%0,%a1
! lay\\t%0,%a1"
[(set_attr "op_type" "RX")
(set_attr "type" "la")])
***************
*** 3344,3350 ****
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
! (match_operand:DF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
--- 3450,3456 ----
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
! (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
***************
*** 3352,3358 ****
(define_insn "*adddf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
! (match_operand:DF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
--- 3458,3464 ----
(define_insn "*adddf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
! (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
***************
*** 3364,3370 ****
(define_insn "*adddf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
! (match_operand:DF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
--- 3470,3476 ----
(define_insn "*adddf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
! (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
***************
*** 3381,3387 ****
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
! (match_operand:SF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
--- 3487,3493 ----
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
! (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
***************
*** 3389,3395 ****
(define_insn "*addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
! (match_operand:SF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
--- 3495,3501 ----
(define_insn "*addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
! (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
***************
*** 3401,3407 ****
(define_insn "*addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
! (match_operand:SF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
--- 3507,3513 ----
(define_insn "*addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
! (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
***************
*** 3428,3434 ****
"@
sgfr\\t%0,%2
sgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_zero_cc"
[(set (reg 33)
--- 3534,3540 ----
"@
sgfr\\t%0,%2
sgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cc"
[(set (reg 33)
***************
*** 3441,3447 ****
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_zero_cconly"
[(set (reg 33)
--- 3547,3553 ----
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cconly"
[(set (reg 33)
***************
*** 3453,3459 ****
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 3559,3565 ----
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 3464,3470 ****
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_cc"
[(set (reg 33)
--- 3570,3576 ----
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cc"
[(set (reg 33)
***************
*** 3477,3483 ****
"@
slgr\\t%0,%2
slg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_cconly"
[(set (reg 33)
--- 3583,3589 ----
"@
slgr\\t%0,%2
slg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cconly"
[(set (reg 33)
***************
*** 3489,3495 ****
"@
slgr\\t%0,%2
slg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 3595,3601 ----
"@
slgr\\t%0,%2
slg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 3550,3631 ****
(define_insn "*subsi3_borrow_cc"
[(set (reg 33)
! (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(match_dup 1)))
! (set (match_operand:SI 0 "register_operand" "=d,d")
(minus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCL2mode)"
"@
slr\\t%0,%2
! sl\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*subsi3_borrow_cconly"
[(set (reg 33)
! (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(match_dup 1)))
! (clobber (match_scratch:SI 0 "=d,d"))]
"s390_match_ccmode(insn, CCL2mode)"
"@
slr\\t%0,%2
! sl\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*subsi3_cc"
[(set (reg 33)
! (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d")
(minus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCLmode)"
"@
slr\\t%0,%2
! sl\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*subsi3_cconly"
[(set (reg 33)
! (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d"))]
"s390_match_ccmode(insn, CCLmode)"
"@
slr\\t%0,%2
! sl\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*subsi3_sign"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (minus:SI (match_operand:SI 1 "register_operand" "0")
! (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
(clobber (reg:CC 33))]
""
! "sh\\t%0,%2"
! [(set_attr "op_type" "RX")])
(define_insn "*subsi3_sub"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (minus:SI (match_operand:SI 1 "register_operand" "0")
! (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
(clobber (reg:CC 33))]
""
! "sh\\t%0,%2"
! [(set_attr "op_type" "RX")])
(define_insn "subsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (minus:SI (match_operand:SI 1 "register_operand" "0,0")
! (match_operand:SI 2 "general_operand" "d,m")))
(clobber (reg:CC 33))]
""
"@
sr\\t%0,%2
! s\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
;
--- 3656,3746 ----
(define_insn "*subsi3_borrow_cc"
[(set (reg 33)
! (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
! (set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCL2mode)"
"@
slr\\t%0,%2
! sl\\t%0,%2
! sly\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_borrow_cconly"
[(set (reg 33)
! (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
! (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCL2mode)"
"@
slr\\t%0,%2
! sl\\t%0,%2
! sly\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXE")])
(define_insn "*subsi3_cc"
[(set (reg 33)
! (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCLmode)"
"@
slr\\t%0,%2
! sl\\t%0,%2
! sly\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_cconly"
[(set (reg 33)
! (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCLmode)"
"@
slr\\t%0,%2
! sl\\t%0,%2
! sly\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_sign"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (minus:SI (match_operand:SI 1 "register_operand" "0,0")
! (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
(clobber (reg:CC 33))]
""
! "@
! sh\\t%0,%2
! shy\\t%0,%2"
! [(set_attr "op_type" "RX,RXY")])
(define_insn "*subsi3_sub"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (minus:SI (match_operand:SI 1 "register_operand" "0,0")
! (subreg:SI (match_operand:HI 2 "memory_operand" "R,T") 0)))
(clobber (reg:CC 33))]
""
! "@
! sh\\t%0,%2
! shy\\t%0,%2"
! [(set_attr "op_type" "RX,RXY")])
(define_insn "subsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d,d")
! (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))]
""
"@
sr\\t%0,%2
! s\\t%0,%2
! sy\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
;
***************
*** 3636,3642 ****
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
! (match_operand:DF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
--- 3751,3757 ----
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
! (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
***************
*** 3644,3650 ****
(define_insn "*subdf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
! (match_operand:DF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
--- 3759,3765 ----
(define_insn "*subdf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
! (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
***************
*** 3656,3662 ****
(define_insn "*subdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
! (match_operand:DF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
--- 3771,3777 ----
(define_insn "*subdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
! (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
***************
*** 3673,3679 ****
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0")
! (match_operand:SF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
--- 3788,3794 ----
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0")
! (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
***************
*** 3681,3687 ****
(define_insn "*subsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0")
! (match_operand:SF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
--- 3796,3802 ----
(define_insn "*subsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0")
! (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
***************
*** 3693,3699 ****
(define_insn "*subsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0")
! (match_operand:SF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
--- 3808,3814 ----
(define_insn "*subsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0")
! (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
***************
*** 3719,3725 ****
"@
msgfr\\t%0,%2
msgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "imul")])
--- 3834,3840 ----
"@
msgfr\\t%0,%2
msgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "imul")])
***************
*** 3732,3738 ****
msgr\\t%0,%2
mghi\\t%0,%h2
msg\\t%0,%2"
! [(set_attr "op_type" "RRE,RI,RXE")
(set_attr "type" "imul")])
;
--- 3847,3853 ----
msgr\\t%0,%2
mghi\\t%0,%h2
msg\\t%0,%2"
! [(set_attr "op_type" "RRE,RI,RXY")
(set_attr "type" "imul")])
;
***************
*** 3740,3754 ****
;
(define_insn "mulsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d,d")
! (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,K,m")))]
""
"@
msr\\t%0,%2
mhi\\t%0,%h2
! ms\\t%0,%2"
! [(set_attr "op_type" "RRE,RI,RX")
(set_attr "type" "imul")])
;
--- 3855,3870 ----
;
(define_insn "mulsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
! (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
! (match_operand:SI 2 "general_operand" "d,K,R,T")))]
""
"@
msr\\t%0,%2
mhi\\t%0,%h2
! ms\\t%0,%2
! msy\\t%0,%2"
! [(set_attr "op_type" "RRE,RI,RX,RXY")
(set_attr "type" "imul")])
;
***************
*** 3781,3787 ****
(mult:DI (sign_extend:DI
(truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
(sign_extend:DI
! (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
"!TARGET_64BIT"
"@
mr\\t%0,%2
--- 3897,3903 ----
(mult:DI (sign_extend:DI
(truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
(sign_extend:DI
! (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
"!TARGET_64BIT"
"@
mr\\t%0,%2
***************
*** 3797,3803 ****
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
! (match_operand:DF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
--- 3913,3919 ----
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
! (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
***************
*** 3805,3811 ****
(define_insn "*muldf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
! (match_operand:DF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
--- 3921,3927 ----
(define_insn "*muldf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
! (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
***************
*** 3817,3823 ****
(define_insn "*muldf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
! (match_operand:DF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
--- 3933,3939 ----
(define_insn "*muldf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
! (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
***************
*** 3834,3840 ****
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
! (match_operand:SF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
--- 3950,3956 ----
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
! (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
***************
*** 3842,3848 ****
(define_insn "*mulsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
! (match_operand:SF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
--- 3958,3964 ----
(define_insn "*mulsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
! (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
***************
*** 3854,3860 ****
(define_insn "*mulsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
! (match_operand:SF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
--- 3970,3976 ----
(define_insn "*mulsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
! (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
***************
*** 3926,3932 ****
"@
dsgr\\t%0,%2
dsg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "idiv")])
(define_insn "divmodtisi3"
--- 4042,4048 ----
"@
dsgr\\t%0,%2
dsg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "idiv")])
(define_insn "divmodtisi3"
***************
*** 3944,3950 ****
"@
dsgfr\\t%0,%2
dsgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "idiv")])
;
--- 4060,4066 ----
"@
dsgfr\\t%0,%2
dsgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "idiv")])
;
***************
*** 4006,4012 ****
"@
dlgr\\t%0,%2
dlg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "idiv")])
;
--- 4122,4128 ----
"@
dlgr\\t%0,%2
dlg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "idiv")])
;
***************
*** 4056,4062 ****
(truncate:SI
(div:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI
! (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
(ashift:DI
(zero_extend:DI
(truncate:SI
--- 4172,4178 ----
(truncate:SI
(div:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI
! (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
(ashift:DI
(zero_extend:DI
(truncate:SI
***************
*** 4266,4272 ****
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0")
! (match_operand:DF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
--- 4382,4388 ----
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0")
! (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
***************
*** 4274,4280 ****
(define_insn "*divdf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0")
! (match_operand:DF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
--- 4390,4396 ----
(define_insn "*divdf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0")
! (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
***************
*** 4286,4292 ****
(define_insn "*divdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0")
! (match_operand:DF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
--- 4402,4408 ----
(define_insn "*divdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0")
! (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
***************
*** 4303,4309 ****
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0")
! (match_operand:SF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
--- 4419,4425 ----
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0")
! (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
***************
*** 4311,4317 ****
(define_insn "*divsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0")
! (match_operand:SF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
--- 4427,4433 ----
(define_insn "*divsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0")
! (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
***************
*** 4323,4329 ****
(define_insn "*divsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0")
! (match_operand:SF 2 "general_operand" "f,m")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
--- 4439,4445 ----
(define_insn "*divsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0")
! (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
***************
*** 4352,4358 ****
"@
ngr\\t%0,%2
ng\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*anddi3_cconly"
[(set (reg 33)
--- 4468,4474 ----
"@
ngr\\t%0,%2
ng\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_cconly"
[(set (reg 33)
***************
*** 4364,4370 ****
"@
ngr\\t%0,%2
ng\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*anddi3_ni"
[(set (match_operand:DI 0 "register_operand" "=d")
--- 4480,4486 ----
"@
ngr\\t%0,%2
ng\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_ni"
[(set (match_operand:DI 0 "register_operand" "=d")
***************
*** 4397,4403 ****
"@
ngr\\t%0,%2
ng\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*anddi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
--- 4513,4519 ----
"@
ngr\\t%0,%2
ng\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
***************
*** 4423,4450 ****
(define_insn "*andsi3_cc"
[(set (reg 33)
! (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d")
(and:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
nr\\t%0,%2
! n\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*andsi3_cconly"
[(set (reg 33)
! (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
nr\\t%0,%2
! n\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*andsi3_ni"
[(set (match_operand:SI 0 "register_operand" "=d")
--- 4539,4568 ----
(define_insn "*andsi3_cc"
[(set (reg 33)
! (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d,d")
(and:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
nr\\t%0,%2
! n\\t%0,%2
! ny\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_cconly"
[(set (reg 33)
! (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
nr\\t%0,%2
! n\\t%0,%2
! ny\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_ni"
[(set (match_operand:SI 0 "register_operand" "=d")
***************
*** 4467,4481 ****
[(set_attr "op_type" "RI")])
(define_insn "andsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m")))
(clobber (reg:CC 33))]
""
"@
nr\\t%0,%2
! n\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*andsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
--- 4585,4600 ----
[(set_attr "op_type" "RI")])
(define_insn "andsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d,d")
! (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))]
""
"@
nr\\t%0,%2
! n\\t%0,%2
! ny\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
***************
*** 4562,4587 ****
[(set_attr "op_type" "RR")])
(define_insn "*andqi3_ss"
! [(set (match_operand:QI 0 "s_operand" "=Q,Q")
(and:QI (match_dup 0)
! (match_operand:QI 1 "s_imm_operand" "n,Q")))
(clobber (reg:CC 33))]
""
"@
ni\\t%0,%b1
nc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")])
(define_insn "*andqi3_ss_inv"
! [(set (match_operand:QI 0 "s_operand" "=Q,Q")
! (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
(match_dup 0)))
(clobber (reg:CC 33))]
""
"@
ni\\t%0,%b1
nc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")])
;;
--- 4681,4708 ----
[(set_attr "op_type" "RR")])
(define_insn "*andqi3_ss"
! [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(and:QI (match_dup 0)
! (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
(clobber (reg:CC 33))]
""
"@
ni\\t%0,%b1
+ niy\\t%0,%b1
nc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*andqi3_ss_inv"
! [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
! (and:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
(match_dup 0)))
(clobber (reg:CC 33))]
""
"@
ni\\t%0,%b1
+ niy\\t%0,%b1
nc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SIY,SS")])
;;
***************
*** 4603,4609 ****
"@
ogr\\t%0,%2
og\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*iordi3_cconly"
[(set (reg 33)
--- 4724,4730 ----
"@
ogr\\t%0,%2
og\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_cconly"
[(set (reg 33)
***************
*** 4615,4621 ****
"@
ogr\\t%0,%2
og\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*iordi3_oi"
[(set (match_operand:DI 0 "register_operand" "=d")
--- 4736,4742 ----
"@
ogr\\t%0,%2
og\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_oi"
[(set (match_operand:DI 0 "register_operand" "=d")
***************
*** 4648,4654 ****
"@
ogr\\t%0,%2
og\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*iordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
--- 4769,4775 ----
"@
ogr\\t%0,%2
og\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
***************
*** 4674,4701 ****
(define_insn "*iorsi3_cc"
[(set (reg 33)
! (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d")
(ior:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
or\\t%0,%2
! o\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*iorsi3_cconly"
[(set (reg 33)
! (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
or\\t%0,%2
! o\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*iorsi3_oi"
[(set (match_operand:SI 0 "register_operand" "=d")
--- 4795,4824 ----
(define_insn "*iorsi3_cc"
[(set (reg 33)
! (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d,d")
(ior:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
or\\t%0,%2
! o\\t%0,%2
! oy\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_cconly"
[(set (reg 33)
! (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
or\\t%0,%2
! o\\t%0,%2
! oy\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_oi"
[(set (match_operand:SI 0 "register_operand" "=d")
***************
*** 4718,4732 ****
[(set_attr "op_type" "RI")])
(define_insn "iorsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m")))
(clobber (reg:CC 33))]
""
"@
or\\t%0,%2
! o\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*iorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
--- 4841,4856 ----
[(set_attr "op_type" "RI")])
(define_insn "iorsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d,d")
! (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))]
""
"@
or\\t%0,%2
! o\\t%0,%2
! oy\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
***************
*** 4813,4838 ****
[(set_attr "op_type" "RR")])
(define_insn "*iorqi3_ss"
! [(set (match_operand:QI 0 "s_operand" "=Q,Q")
(ior:QI (match_dup 0)
! (match_operand:QI 1 "s_imm_operand" "n,Q")))
(clobber (reg:CC 33))]
""
"@
oi\\t%0,%b1
oc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")])
(define_insn "*iorqi3_ss_inv"
! [(set (match_operand:QI 0 "s_operand" "=Q,Q")
! (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
(match_dup 0)))
(clobber (reg:CC 33))]
""
"@
oi\\t%0,%b1
oc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")])
;;
--- 4937,4964 ----
[(set_attr "op_type" "RR")])
(define_insn "*iorqi3_ss"
! [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(ior:QI (match_dup 0)
! (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
(clobber (reg:CC 33))]
""
"@
oi\\t%0,%b1
+ oiy\\t%0,%b1
oc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*iorqi3_ss_inv"
! [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
! (ior:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
(match_dup 0)))
(clobber (reg:CC 33))]
""
"@
oi\\t%0,%b1
+ oiy\\t%0,%b1
oc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SIY,SS")])
;;
***************
*** 4854,4860 ****
"@
xgr\\t%0,%2
xg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*xordi3_cconly"
[(set (reg 33)
--- 4980,4986 ----
"@
xgr\\t%0,%2
xg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*xordi3_cconly"
[(set (reg 33)
***************
*** 4866,4872 ****
"@
xgr\\t%0,%2
xr\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "xordi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 4992,4998 ----
"@
xgr\\t%0,%2
xr\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "xordi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 4877,4883 ****
"@
xgr\\t%0,%2
xg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*xordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
--- 5003,5009 ----
"@
xgr\\t%0,%2
xg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXY")])
(define_insn "*xordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
***************
*** 4903,4941 ****
(define_insn "*xorsi3_cc"
[(set (reg 33)
! (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d")
(xor:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
xr\\t%0,%2
! x\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*xorsi3_cconly"
[(set (reg 33)
! (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m"))
(const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
xr\\t%0,%2
! x\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "xorsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
! (match_operand:SI 2 "general_operand" "d,m")))
(clobber (reg:CC 33))]
""
"@
xr\\t%0,%2
! x\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*xorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
--- 5029,5070 ----
(define_insn "*xorsi3_cc"
[(set (reg 33)
! (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d,d")
(xor:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
xr\\t%0,%2
! x\\t%0,%2
! xy\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*xorsi3_cconly"
[(set (reg 33)
! (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
xr\\t%0,%2
! x\\t%0,%2
! xy\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "xorsi3"
! [(set (match_operand:SI 0 "register_operand" "=d,d,d")
! (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
! (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))]
""
"@
xr\\t%0,%2
! x\\t%0,%2
! xy\\t%0,%2"
! [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*xorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
***************
*** 4966,4973 ****
(clobber (reg:CC 33))]
""
"xr\\t%0,%2"
! [(set_attr "op_type" "RR")
! (set_attr "atype" "reg")])
(define_insn "*xorhi3_ss"
[(set (match_operand:HI 0 "s_operand" "=Q")
--- 5095,5101 ----
(clobber (reg:CC 33))]
""
"xr\\t%0,%2"
! [(set_attr "op_type" "RR")])
(define_insn "*xorhi3_ss"
[(set (match_operand:HI 0 "s_operand" "=Q")
***************
*** 5001,5026 ****
[(set_attr "op_type" "RR")])
(define_insn "*xorqi3_ss"
! [(set (match_operand:QI 0 "s_operand" "=Q,Q")
(xor:QI (match_dup 0)
! (match_operand:QI 1 "s_imm_operand" "n,Q")))
(clobber (reg:CC 33))]
""
"@
xi\\t%0,%b1
xc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")])
(define_insn "*xorqi3_ss_inv"
! [(set (match_operand:QI 0 "s_operand" "=Q,Q")
! (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
(match_dup 0)))
(clobber (reg:CC 33))]
""
"@
xi\\t%0,%b1
xc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")])
;;
--- 5129,5156 ----
[(set_attr "op_type" "RR")])
(define_insn "*xorqi3_ss"
! [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(xor:QI (match_dup 0)
! (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
(clobber (reg:CC 33))]
""
"@
xi\\t%0,%b1
+ xiy\\t%0,%b1
xc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*xorqi3_ss_inv"
! [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
! (xor:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
(match_dup 0)))
(clobber (reg:CC 33))]
""
"@
xi\\t%0,%b1
+ xiy\\t%0,%b1
xc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SIY,SS")])
;;
***************
*** 5239,5251 ****
(define_insn "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "=f,f")
! (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sqdbr\\t%0,%1
sqdb\\t%0,%1"
! [(set_attr "op_type" "RRE,RSE")
! (set_attr "type" "fsqrtd")])
;
; sqrtsf2 instruction pattern(s).
--- 5369,5380 ----
(define_insn "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "=f,f")
! (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sqdbr\\t%0,%1
sqdb\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")])
;
; sqrtsf2 instruction pattern(s).
***************
*** 5253,5265 ****
(define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f,f")
! (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sqebr\\t%0,%1
sqeb\\t%0,%1"
! [(set_attr "op_type" "RRE,RSE")
! (set_attr "type" "fsqrts")])
;;
;;- One complement instructions.
--- 5382,5393 ----
(define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f,f")
! (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sqebr\\t%0,%1
sqeb\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")])
;;
;;- One complement instructions.
***************
*** 5796,5802 ****
[(set (pc)
(if_then_else
(match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
! (match_operand 0 "address_operand" "p")
(pc)))]
""
"*
--- 5924,5930 ----
[(set (pc)
(if_then_else
(match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
! (match_operand 0 "address_operand" "U")
(pc)))]
""
"*
***************
*** 5848,5854 ****
(if_then_else
(match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
(pc)
! (match_operand 0 "address_operand" "p")))]
""
"*
{
--- 5976,5982 ----
(if_then_else
(match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
(pc)
! (match_operand 0 "address_operand" "U")))]
""
"*
{
***************
*** 5961,5967 ****
(if_then_else
(ne (match_operand:SI 1 "register_operand" "d,d")
(const_int 1))
! (match_operand 0 "address_operand" "p,p")
(pc)))
(set (match_operand:SI 2 "register_operand" "=1,?*m*d")
(plus:SI (match_dup 1) (const_int -1)))
--- 6089,6095 ----
(if_then_else
(ne (match_operand:SI 1 "register_operand" "d,d")
(const_int 1))
! (match_operand 0 "address_operand" "U,U")
(pc)))
(set (match_operand:SI 2 "register_operand" "=1,?*m*d")
(plus:SI (match_dup 1) (const_int -1)))
***************
*** 6037,6043 ****
(if_then_else
(ne (match_operand:DI 1 "register_operand" "d,d")
(const_int 1))
! (match_operand 0 "address_operand" "p,p")
(pc)))
(set (match_operand:DI 2 "register_operand" "=1,?*m*d")
(plus:DI (match_dup 1) (const_int -1)))
--- 6165,6171 ----
(if_then_else
(ne (match_operand:DI 1 "register_operand" "d,d")
(const_int 1))
! (match_operand 0 "address_operand" "U,U")
(pc)))
(set (match_operand:DI 2 "register_operand" "=1,?*m*d")
(plus:DI (match_dup 1) (const_int -1)))
***************
*** 6116,6122 ****
;
(define_insn "indirect_jump"
! [(set (pc) (match_operand 0 "address_operand" "p"))]
""
"*
{
--- 6244,6250 ----
;
(define_insn "indirect_jump"
! [(set (pc) (match_operand 0 "address_operand" "U"))]
""
"*
{
***************
*** 6136,6142 ****
;
(define_insn "casesi_jump"
! [(set (pc) (match_operand 0 "address_operand" "p"))
(use (label_ref (match_operand 1 "" "")))]
""
"*
--- 6264,6270 ----
;
(define_insn "casesi_jump"
! [(set (pc) (match_operand 0 "address_operand" "U"))
(use (label_ref (match_operand 1 "" "")))]
""
"*
***************
*** 6342,6348 ****
(set_attr "atype" "agen")])
(define_insn "bas_64"
! [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
(match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:DI 2 "register_operand" "=r"))]
"TARGET_64BIT"
--- 6470,6476 ----
(set_attr "atype" "agen")])
(define_insn "bas_64"
! [(call (mem:QI (match_operand:QI 0 "address_operand" "U"))
(match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:DI 2 "register_operand" "=r"))]
"TARGET_64BIT"
***************
*** 6351,6357 ****
(set_attr "type" "jsr")])
(define_insn "bas_31"
! [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
(match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:SI 2 "register_operand" "=r"))]
"!TARGET_64BIT"
--- 6479,6485 ----
(set_attr "type" "jsr")])
(define_insn "bas_31"
! [(call (mem:QI (match_operand:QI 0 "address_operand" "U"))
(match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:SI 2 "register_operand" "=r"))]
"!TARGET_64BIT"
***************
*** 6468,6474 ****
(define_insn "bas_r_64"
[(set (match_operand 0 "register_operand" "=df")
! (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:DI 3 "register_operand" "=r"))]
"TARGET_64BIT"
--- 6596,6602 ----
(define_insn "bas_r_64"
[(set (match_operand 0 "register_operand" "=df")
! (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:DI 3 "register_operand" "=r"))]
"TARGET_64BIT"
***************
*** 6478,6484 ****
(define_insn "bas_r_31"
[(set (match_operand 0 "register_operand" "=df")
! (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:SI 3 "register_operand" "=r"))]
"!TARGET_64BIT"
--- 6606,6612 ----
(define_insn "bas_r_31"
[(set (match_operand 0 "register_operand" "=df")
! (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:SI 3 "register_operand" "=r"))]
"!TARGET_64BIT"
***************
*** 6542,6554 ****
[(set_attr "op_type" "RXE")])
(define_insn "*tls_load_31"
! [(set (match_operand:SI 0 "register_operand" "=d")
! (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
(match_operand:SI 2 "" "")]
UNSPEC_TLS_LOAD))]
"!TARGET_64BIT"
! "l\\t%0,%1%J2"
! [(set_attr "op_type" "RX")])
(define_expand "call_value_tls"
[(set (match_operand 0 "" "")
--- 6670,6684 ----
[(set_attr "op_type" "RXE")])
(define_insn "*tls_load_31"
! [(set (match_operand:SI 0 "register_operand" "=d,d")
! (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
(match_operand:SI 2 "" "")]
UNSPEC_TLS_LOAD))]
"!TARGET_64BIT"
! "@
! l\\t%0,%1%J2
! ly\\t%0,%1%J2"
! [(set_attr "op_type" "RX,RXY")])
(define_expand "call_value_tls"
[(set (match_operand 0 "" "")
***************
*** 6648,6654 ****
(define_insn "bas_tls_64"
[(set (match_operand 0 "register_operand" "=df")
! (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:DI 3 "register_operand" "=r"))
(use (match_operand:DI 4 "" ""))]
--- 6778,6784 ----
(define_insn "bas_tls_64"
[(set (match_operand 0 "register_operand" "=df")
! (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:DI 3 "register_operand" "=r"))
(use (match_operand:DI 4 "" ""))]
***************
*** 6660,6666 ****
(define_insn "bas_tls_31"
[(set (match_operand 0 "register_operand" "=df")
! (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:SI 3 "register_operand" "=r"))
(use (match_operand:SI 4 "" ""))]
--- 6790,6796 ----
(define_insn "bas_tls_31"
[(set (match_operand 0 "register_operand" "=df")
! (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:SI 3 "register_operand" "=r"))
(use (match_operand:SI 4 "" ""))]
--
Dr. Ulrich Weigand
weigand@informatik.uni-erlangen.de