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[patch] Follow spelling conventions.


Hi,

Attached is a patch to follow spelling conventions.

Committed as obvious.

Kazu Hirata

2003-06-28  Kazu Hirata  <kazu@cs.umass.edu>

	* builtins.c: Follow spelling conventions.
	* cgraph.c: Likewise.
	* cpplex.c: Likewise.
	* config/arm/arm.c: Likewise.
	* config/arm/iwmmxt.md: Likewise.
	* config/c4x/c4x-modes.def: Likewise.
	* config/c4x/c4x.c: Likewise.
	* config/c4x/c4x.h: Likewise.
	* config/c4x/c4x.md: Likewise.
	* config/i386/i386-interix.h: Likewise.
	* config/mips/mips.h: Likewise.

Index: builtins.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/builtins.c,v
retrieving revision 1.227
diff -u -r1.227 builtins.c
--- builtins.c	28 Jun 2003 12:21:13 -0000	1.227
+++ builtins.c	28 Jun 2003 19:18:24 -0000
@@ -242,9 +242,9 @@
    way, because it could contain a zero byte in the middle.
    TREE_STRING_LENGTH is the size of the character array, not the string.
 
-   ONLY_VALUE should be non-zero if the result is not going to be emitted
+   ONLY_VALUE should be nonzero if the result is not going to be emitted
    into the instruction stream and zero if it is going to be expanded.
-   E.g. with i++ ? "foo" : "bar", if ONLY_VALUE is non-zero, constant 3
+   E.g. with i++ ? "foo" : "bar", if ONLY_VALUE is nonzero, constant 3
    is returned, otherwise NULL, since
    len = c_strlen (src, 1); if (len) expand_expr (len, ...); would not
    evaluate the side-effects.
Index: cgraph.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/cgraph.c,v
retrieving revision 1.14
diff -u -r1.14 cgraph.c
--- cgraph.c	27 Jun 2003 15:42:48 -0000	1.14
+++ cgraph.c	28 Jun 2003 19:18:25 -0000
@@ -373,7 +373,7 @@
 		       (((struct cgraph_varpool_node *) p)->decl));
 }
 
-/* Returns non-zero if P1 and P2 are equal.  */
+/* Returns nonzero if P1 and P2 are equal.  */
 
 static int
 eq_cgraph_varpool_node (const PTR p1, const PTR p2)
Index: cpplex.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/cpplex.c,v
retrieving revision 1.239
diff -u -r1.239 cpplex.c
--- cpplex.c	17 Jun 2003 06:17:43 -0000	1.239
+++ cpplex.c	28 Jun 2003 19:18:28 -0000
@@ -746,7 +746,7 @@
    get diagnostics pointing to the correct location.
 
    Does not handle issues such as token lookahead, multiple-include
-   optimisation, directives, skipping etc.  This function is only
+   optimization, directives, skipping etc.  This function is only
    suitable for use by _cpp_lex_token, and in special cases like
    lex_expansion_token which doesn't care for any of these issues.
 
Index: config/arm/arm.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.c,v
retrieving revision 1.285
diff -u -r1.285 arm.c
--- config/arm/arm.c	19 Jun 2003 21:47:04 -0000	1.285
+++ config/arm/arm.c	28 Jun 2003 19:18:32 -0000
@@ -2094,7 +2094,7 @@
       TREE_SIDE_EFFECTS (t) = 1;
       expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
 
-      /* This is to stop the combine pass optimising
+      /* This is to stop the combine pass optimizing
 	 away the alignment adjustment.  */
       mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
     }
Index: config/arm/iwmmxt.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/iwmmxt.md,v
retrieving revision 1.1
diff -u -r1.1 iwmmxt.md
--- config/arm/iwmmxt.md	18 Jun 2003 16:36:12 -0000	1.1
+++ config/arm/iwmmxt.md	28 Jun 2003 19:18:33 -0000
@@ -185,7 +185,7 @@
    (set_attr "neg_pool_range" "*,     *, 244,*,*, 244")])
 
 ;; This pattern should not be needed.  It is to match a
-;; wierd case generated by GCC when no optimisations are
+;; wierd case generated by GCC when no optimizations are
 ;; enabled.  (Try compiling gcc/testsuite/gcc.c-torture/
 ;; compile/simd-5.c at -O0).  The mode for operands[1] is
 ;; deliberately omitted.
Index: config/c4x/c4x-modes.def
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/c4x/c4x-modes.def,v
retrieving revision 1.2
diff -u -r1.2 c4x-modes.def
--- config/c4x/c4x-modes.def	13 Mar 2003 04:06:49 -0000	1.2
+++ config/c4x/c4x-modes.def	28 Jun 2003 19:18:33 -0000
@@ -25,7 +25,7 @@
 
    On the C4x, we have a "no-overflow" mode which is used when an ADD,
    SUB, NEG, or MPY insn is used to set the condition code.  This is
-   to prevent the combiner from optimising away a following CMP of the
+   to prevent the combiner from optimizing away a following CMP of the
    result with zero when a signed conditional branch or load insn
    follows.
 
Index: config/c4x/c4x.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/c4x/c4x.c,v
retrieving revision 1.129
diff -u -r1.129 c4x.c
--- config/c4x/c4x.c	19 Jun 2003 21:47:07 -0000	1.129
+++ config/c4x/c4x.c	28 Jun 2003 19:18:34 -0000
@@ -1692,7 +1692,7 @@
 
 /* Provide the costs of an addressing mode that contains ADDR.
    If ADDR is not a valid address, its cost is irrelevant.  
-   This is used in cse and loop optimisation to determine
+   This is used in cse and loop optimization to determine
    if it is worthwhile storing a common address into a register. 
    Unfortunately, the C4x address cost depends on other operands.  */
 
@@ -2437,7 +2437,7 @@
 
 /* We need to use direct addressing for large constants and addresses
    that cannot fit within an instruction.  We must check for these
-   after after the final jump optimisation pass, since this may
+   after after the final jump optimization pass, since this may
    introduce a local_move insn for a SYMBOL_REF.  This pass
    must come before delayed branch slot filling since it can generate
    additional instructions.
@@ -3642,7 +3642,7 @@
 	 cause problems except when writing to a hardware device such
 	 as a FIFO since the second write will be lost.  The user
 	 should flag the hardware location as being volatile so that
-	 we don't do this optimisation.  While it is unlikely that we
+	 we don't do this optimization.  While it is unlikely that we
 	 have an aliased address if both locations are not marked
 	 volatile, it is probably safer to flag a potential conflict
 	 if either location is volatile.  */
@@ -4034,7 +4034,7 @@
       /* During RTL generation, force constants into pseudos so that
 	 they can get hoisted out of loops.  This will tie up an extra
 	 register but can save an extra cycle.  Only do this if loop
-	 optimisation enabled.  (We cannot pull this trick for add and
+	 optimization enabled.  (We cannot pull this trick for add and
 	 sub instructions since the flow pass won't find
 	 autoincrements etc.)  This allows us to generate compare
 	 instructions like CMPI R0, *AR0++ where R0 = 42, say, instead
Index: config/c4x/c4x.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/c4x/c4x.h,v
retrieving revision 1.132
diff -u -r1.132 c4x.h
--- config/c4x/c4x.h	19 Jun 2003 21:47:07 -0000	1.132
+++ config/c4x/c4x.h	28 Jun 2003 19:18:36 -0000
@@ -775,7 +775,7 @@
    is defined since the MPY|ADD insns require the classes R0R1_REGS and
    R2R3_REGS which are used by the function return registers (R0,R1) and
    the register arguments (R2,R3), respectively.  I'm reluctant to define
-   this macro since it stomps on many potential optimisations.  Ideally
+   this macro since it stomps on many potential optimizations.  Ideally
    it should have a register class argument so that not all the register
    classes gets penalised for the sake of a naughty few...  For long
    double arithmetic we need two additional registers that we can use as
Index: config/c4x/c4x.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/c4x/c4x.md,v
retrieving revision 1.77
diff -u -r1.77 c4x.md
--- config/c4x/c4x.md	13 Mar 2003 04:06:50 -0000	1.77
+++ config/c4x/c4x.md	28 Jun 2003 19:18:38 -0000
@@ -3127,9 +3127,9 @@
 ; Unfortunately the C40 doesn't allow cmpi3 7, *ar0++ so the next best
 ; thing would be to get the small constant loaded into a register (say r0)
 ; so that it could be hoisted out of the loop so that we only
-; would need to do cmpi3 *ar0++, r0.  Now the loop optimisation pass
+; would need to do cmpi3 *ar0++, r0.  Now the loop optimization pass
 ; comes before the flow pass (which finds autoincrements) so we're stuck.
-; Ideally, GCC requires another loop optimisation pass (preferably after
+; Ideally, GCC requires another loop optimization pass (preferably after
 ; reload) so that it can hoist invariants out of loops.
 ; The current solution modifies legitimize_operands () so that small
 ; constants are forced into a pseudo register.
Index: config/i386/i386-interix.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386-interix.h,v
retrieving revision 1.41
diff -u -r1.41 i386-interix.h
--- config/i386/i386-interix.h	19 Jun 2003 21:47:11 -0000	1.41
+++ config/i386/i386-interix.h	28 Jun 2003 19:18:38 -0000
@@ -236,7 +236,7 @@
 #define TARGET_NOP_FUN_DLLIMPORT 1
 #define drectve_section()  /* nothing */
 
-/* Objective C has its own packing rules...
+/* Objective-C has its own packing rules...
    Objc tries to parallel the code in stor-layout.c at runtime	
    (see libobjc/encoding.c).  This (compile-time) packing info isn't 
    available at runtime, so it's hopeless to try.
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.267
diff -u -r1.267 mips.h
--- config/mips/mips.h	20 Jun 2003 12:16:26 -0000	1.267
+++ config/mips/mips.h	28 Jun 2003 19:18:41 -0000
@@ -3166,7 +3166,7 @@
 
 
 /* The cost of loading values from the constant pool.  It should be
-   larger than the cost of any constant we want to synthesise in-line.  */
+   larger than the cost of any constant we want to synthesize in-line.  */
 
 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
 


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