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RE: [PATCH] Enable push_fpscr. pop_fpscr for SH2E


Hi,

> 2003-01-31 Dhananjay Deshpande <dhananjayd@kpit.com>

> 	* gcc/config/sh/sh.md  (define_expand "push_fpscr"): Enable for 	TARGET_SH2E.
> 	(define_expand "pop_fpscr"): Likewise.
> 	(define_insn "fpu_switch"): Likewise.

>Thanks, this looks correct, but I'm wondering if we shouldn't instead
>only enable these opcodes for SH4, since we never use them unless we
>do mode switching, which we only do on CPUs that actually support both
>modes.  Jörn, comments?

fpu_switch is used for mode switching only for SH4. But sometime last year a patch enabled fpscr to be pushed in interrupt handler if it is live which requires push and pop fpscr patterns. Please refer to the discussion in Nov/Dec 2002 on gcc-patches mailing list. 

Regards,
Dhananjay

> ==========================================================================
> --- sh.md.old	Fri Jan 31 11:02:45 2003
> +++ sh.md	Fri Jan 31 11:03:30 2003
> @@ -3340,7 +3340,7 @@
 
>  (define_expand "push_fpscr"
>    [(const_int 0)]
> -  "TARGET_SH3E"
> +  "TARGET_SH2E"
>    "
>  {
>    rtx insn = emit_insn (gen_fpu_switch (gen_rtx (MEM, PSImode,
> @@ -3353,7 +3353,7 @@
 
>  (define_expand "pop_fpscr"
>    [(const_int 0)]
> -  "TARGET_SH3E"
> +  "TARGET_SH2E"
>    "
>  {
>    rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
> @@ -7889,7 +7889,7 @@
>  (define_insn "fpu_switch"
>    [(set (match_operand:PSI 0 "general_movdst_operand" "=c,c,r,c,c,r,m,r,<")
>  	(match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c,c"))]
> -  "TARGET_SH3E
> +  "TARGET_SH2E
>     && (! reload_completed
>         || true_regnum (operands[0]) != FPSCR_REG
>         || GET_CODE (operands[1]) != MEM

-- 
Alexandre Oliva   Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer                 aoliva@{redhat.com, gcc.gnu.org}
CS PhD student at IC-Unicamp        oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist                Professional serial bug killer


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