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Re: [PATCH] Fix PR optimization/10876
- From: kenner at vlsi1 dot ultra dot nyu dot edu (Richard Kenner)
- To: ebotcazou at libertysurf dot fr
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Sun, 25 May 03 14:10:55 EDT
- Subject: Re: [PATCH] Fix PR optimization/10876
Uh... I fail to see the logic, probably because I again badly explained
myself. What I want to say is that you can't write
add %i0, 4096, %i0
whereas you can write
sub %i0, -4096, %i0
in SPARC language.
Yes, of course. But the point is that the RTL representation for both
is (plus (reg) (const_int 4096)): the code that writes the insn has to
know whether to use "add" or "sub".
Let me try to explain in another way:
Suppose we have a machine that has a two-bit immediate field which is
interpreted as unsigned and has ADD and SUB instructions with such a
field. That machine can support
(plus (reg) (const_int X))
for X = -3, -2, -1, 0, 1, 2, and 3. For the first three values of X, the
addsi3 pattern writes an opcode of SUB and writes ADD for the last three.