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ARM PATCH add patterns for merging scc operands


This patch allows combine to merge some scc insns by using conditional 
comparisons.  For example,

int g (int x, int y)
{  return x >= 0 && y > 0;
}

Is now compiled to 

        cmp     r0, #0
        cmpge   r1, #0
        movle   r0, #0
        movgt   r0, #1
        mov     pc, lr

When previously it generated

        cmp     r1, #0
        movle   r1, #0
        movgt   r1, #1
        cmp     r0, #0
        movlt   r0, #0
        andge   r0, r1, #1
        mov     pc, lr

Prior to this patch, the merging would only occur if the sequence was 
immediately followed by a conditional branch.

There are some comparisons where we could do better still (see the recent 
CLZ discussion), but this fixes the most gratuitously bad cases.

2003-05-10  Richard Earnshaw  <rearnsha@arm.com>

	* arm.md (DOM_CC_X_AND_Y, DOM_CC_NX_OR_Y, DOM_CC_X_OR_Y): New 
	constants.
	(ior_scc_scc, and_scc_scc): New insn_and_split patterns.
	* arm.c (arm_select_dominance_cc_mode): Renamed from 
	select_dominance_cc_mode, no-longer static.  Use DOM_CC... constants.
	Callers updated.
	* arm-protos.h (arm_select_dominance_cc_mode): Add prototype.


Attachment: dompred.patch
Description: dompred.patch


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