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[PATCH] Display all the target switches for SH compiler's '--target-help' option


Hi All,

The SH compiler displays only few target switches when given the '--target-help' option.
Following is the patch to display all of the target switches.

gcc/ChangeLog
2003-05-09 Rekha Bhintade <rekhad@kpitcummins.com>

	* gcc/config/sh/sh.h (TARGET_SWITCHES): Display all the target switches when --target-help option is specified. 

============================================================================================
*** gcc/gcc/config/sh/sh.h.orig	Thu May  8 16:16:55 2003
--- gcc/gcc/config/sh/sh.h	Fri May  9 16:31:54 2003
***************
*** 281,301 ****
  #define TARGET_SWITCHES  			\
  { {"1",	        TARGET_NONE, "" },		\
!   {"1",	        SELECT_SH1, "" },		\
    {"2",	        TARGET_NONE, "" },		\
!   {"2",	        SELECT_SH2, "" },		\
    {"2e",        TARGET_NONE, "" },		\
!   {"2e",        SELECT_SH2E, "" },		\
    {"3",	        TARGET_NONE, "" },		\
!   {"3",	        SELECT_SH3, "" },		\
    {"3e",	TARGET_NONE, "" },		\
!   {"3e",	SELECT_SH3E, "" },		\
    {"4-single-only",	TARGET_NONE, "" },	\
!   {"4-single-only",	SELECT_SH4_SINGLE_ONLY, "" },	\
    {"4-single",	TARGET_NONE, "" },		\
!   {"4-single",	SELECT_SH4_SINGLE, "" },	\
    {"4-nofpu",	TARGET_NONE, "" },		\
!   {"4-nofpu",	SELECT_SH4_NOFPU, "" },		\
    {"4",	        TARGET_NONE, "" },		\
!   {"4",	        SELECT_SH4, "" }, 		\
    {"5-64media",	TARGET_NONE, "" },		\
    {"5-64media", SELECT_SH5_64, "Generate 64-bit SHmedia code" }, \
--- 281,301 ----
  #define TARGET_SWITCHES  			\
  { {"1",	        TARGET_NONE, "" },		\
!   {"1",	        SELECT_SH1, "Generate SH1 code" },		\
    {"2",	        TARGET_NONE, "" },		\
!   {"2",	        SELECT_SH2, "Generate SH2 code" },		\
    {"2e",        TARGET_NONE, "" },		\
!   {"2e",        SELECT_SH2E, "Generate SH2e code" },		\
    {"3",	        TARGET_NONE, "" },		\
!   {"3",	        SELECT_SH3, "Generate SH3 code" },		\
    {"3e",	TARGET_NONE, "" },		\
!   {"3e",	SELECT_SH3E, "Generate SH3e code" },		\
    {"4-single-only",	TARGET_NONE, "" },	\
!   {"4-single-only",	SELECT_SH4_SINGLE_ONLY, "Generate only single-precision SH4 code" },	\
    {"4-single",	TARGET_NONE, "" },		\
!   {"4-single",	SELECT_SH4_SINGLE, "Generate default single-precision SH4 code" },	\
    {"4-nofpu",	TARGET_NONE, "" },		\
!   {"4-nofpu",	SELECT_SH4_NOFPU, "Generate SH4 FPU-less code" },		\
    {"4",	        TARGET_NONE, "" },		\
!   {"4",	        SELECT_SH4, "Generate SH4 code" }, 		\
    {"5-64media",	TARGET_NONE, "" },		\
    {"5-64media", SELECT_SH5_64, "Generate 64-bit SHmedia code" }, \
***************
*** 310,328 ****
    {"5-compact-nofpu", TARGET_NONE, "" },	\
    {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" }, \
!   {"b",		-LITTLE_ENDIAN_BIT, "" },  	\
!   {"bigtable", 	BIGTABLE_BIT, "" },		\
!   {"dalign",  	DALIGN_BIT, "" },		\
!   {"fmovd",  	FMOVD_BIT, "" },		\
!   {"hitachi",	HITACHI_BIT, "" },		\
!   {"nomacsave", NOMACSAVE_BIT, "" },		\
!   {"ieee",  	IEEE_BIT, "" },			\
!   {"isize", 	ISIZE_BIT, "" },		\
!   {"l",		LITTLE_ENDIAN_BIT, "" },  	\
    {"no-ieee",  	-IEEE_BIT, "" },		\
    {"padstruct", PADSTRUCT_BIT, "" },    	\
!   {"prefergot",	PREFERGOT_BIT, "" },		\
!   {"relax",	RELAX_BIT, "" },		\
!   {"space", 	SPACE_BIT, "" },		\
!   {"usermode",	USERMODE_BIT, "" },		\
    SUBTARGET_SWITCHES                            \
    {"",   	TARGET_DEFAULT, "" } 		\
--- 310,328 ----
    {"5-compact-nofpu", TARGET_NONE, "" },	\
    {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" }, \
!   {"b",		-LITTLE_ENDIAN_BIT, "Generate code in big endian mode" },  	\
!   {"bigtable", 	BIGTABLE_BIT, "Generate 32-bit offsets in switch tables" },		\
!   {"dalign",  	DALIGN_BIT, "Aligns doubles at 64-bit boundaries" },		\
!   {"fmovd",  	FMOVD_BIT, "Enable instruction fmovd" },		\
!   {"hitachi",	HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" },		\
!   {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" },		\
!   {"ieee",  	IEEE_BIT, "Increase the IEEE compliance for floating-point code" },			\
!   {"isize", 	ISIZE_BIT, "Dump instruction size and location in the assembly code" },		\
!   {"l",		LITTLE_ENDIAN_BIT, "Generate code in little endian mode" },  	\
    {"no-ieee",  	-IEEE_BIT, "" },		\
    {"padstruct", PADSTRUCT_BIT, "" },    	\
!   {"prefergot",	PREFERGOT_BIT, "Emit function-calls using global offset table when generating PIC" },		\
!   {"relax",	RELAX_BIT, "Shorten address references during linking" },		\
!   {"space", 	SPACE_BIT, "Optimize for space instead of speed" },		\
!   {"usermode",	USERMODE_BIT, "Generate library function call to invalidate instruction cache entries after fixing trampoline" },		\
    SUBTARGET_SWITCHES                            \
    {"",   	TARGET_DEFAULT, "" } 		\

Thanks & regards,
Rekha Bhintade
KPIT Cummins Infosystem Ltd.




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