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RFA: Add SH2E support
- From: Nick Clifton <nickc at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: 23 Jan 2003 18:56:59 +0000
- Subject: RFA: Add SH2E support
Hi Guys,
I am contributing the SH2E port developed by Red Hat. May I have
permission to apply the patch below to update gcc please ?
Cheers
Nick
gcc/ChangeLog
2003-01-23 Nick Clifton <nickc@redhat.com>
* Add sh2e support:
2002-08-12 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (output_branch) [TARGET_SH2E]: Handle
med_cbranches. Fix logic in short_cbranches.
2002-04-03 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (delay for cbranch): Don't annul delay
slots on SH2e.
* config/sh/sh.c (sh_insn_length_adjustment): Add 2 for
cbranch with unfilled delay slot on SH2e.
(output_branch): Fill with a nop the delay slot of a
branch that required a delay slot but didn't get one.
2002-04-02 Alexandre Oliva <aoliva@redhat.com>
* doc/invoke.texi (SH options): Document -m2e.
* config/float-sh.h: Make sh2e doubles equivalent to floats.
* config/sh/crt1.asm: Add __SH2E__ Next to __SH3E__.
* config/sh/lib1funcs.asm: Likewise.
* config/sh/sh.c: Replace all uses of TARGET_SH3E with SH2E.
* config/sh/sh.h (CPP_SPEC): Define __SH2E__ for -m2e, and
not __sh1__.
(CONDITIONAL_REGISTER_USAGE): Don't disable FP regs from
SH2E up.
(SH3E_BIT): Renamed to...
(SH_E_BIT): ... this. Replace all uses.
(TARGET_SH2E): Define from SH_E_BIT and TARGET_SH2.
Replace all uses of TARGET_SH3E with TARGET_SH2E.
(TARGET_SWITCHES): Added 2e.
(OVERRIDE_OPTIONS): Set sh_cpu for SH2E.
(processor_type): Added PROCESSOR_SH2E.
* config/sh/sh.md: Replace all uses of TARGET_SH3E with
TARGET_SH2E, except in sqrtsf2_i.
(attribute cpu): Added sh2e.
* config/sh/t-sh (MULTILIB_OPTIONS): Replace m3e with m2e.
(MULTILIB_MATCHES): Use m2e multilib for m3e.
* config.gcc: Add sh2e target support.
Index: gcc/config.gcc
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config.gcc,v
retrieving revision 1.275
diff -c -3 -p -w -r1.275 config.gcc
*** gcc/config.gcc 19 Jan 2003 13:04:21 -0000 1.275
--- gcc/config.gcc 23 Jan 2003 18:25:59 -0000
*************** sh-*-elf* | sh[2346l]*-*-elf*)
*** 2207,2212 ****
--- 2207,2213 ----
sh4*) target_cpu_default="SELECT_SH4" ;;
sh3e*) target_cpu_default="SELECT_SH3E" ;;
sh3*) target_cpu_default="SELECT_SH3" ;;
+ sh2e*) target_cpu_default="SELECT_SH2E" ;;
sh2*) target_cpu_default="SELECT_SH2" ;;
esac
case $machine in
*************** sh-*-linux* | sh[2346lbe]*-*-linux*)
*** 2251,2256 ****
--- 2252,2260 ----
sh3e[lb]*) target_cpu_default="SELECT_SH3" ;;
sh3e*) target_cpu_default="SELECT_SH3E" ;;
sh3*) target_cpu_default="SELECT_SH3" ;;
+ sh2e[lb]e*) target_cpu_default="SELECT_SH2E" ;;
+ sh2e[lb]*) target_cpu_default="SELECT_SH2" ;;
+ sh2e*) target_cpu_default="SELECT_SH2E" ;;
sh2*) target_cpu_default="SELECT_SH2" ;;
esac
case $machine in
*************** sh-*-netbsdelf* | shl*-*-netbsdelf* | sh
*** 2273,2279 ****
case $machine in
sh5*-*)
# SHmedia, 32-bit ABI
! target_cpu_default="SH5_BIT|SH4_BIT|SH3E_BIT"
tmake_file="${tmake_file} sh/t-sh64 sh/t-netbsd-sh5"
;;
sh64*-*)
--- 2277,2283 ----
case $machine in
sh5*-*)
# SHmedia, 32-bit ABI
! target_cpu_default="SH5_BIT|SH4_BIT|SH3_BIT|SH_E_BIT"
tmake_file="${tmake_file} sh/t-sh64 sh/t-netbsd-sh5"
;;
sh64*-*)
Index: gcc/config/sh/crt1.asm
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/crt1.asm,v
retrieving revision 1.6
diff -c -3 -p -w -r1.6 crt1.asm
*** gcc/config/sh/crt1.asm 26 Jun 2002 15:42:03 -0000 1.6
--- gcc/config/sh/crt1.asm 23 Jan 2003 18:26:18 -0000
*************** start_l:
*** 116,127 ****
cmp/ge r0,r1
bt start_l
! #if defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
mov.l set_fpscr_k, r1
jsr @r1
mov #0,r4
lds r3,fpscr
! #endif /* defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) */
! arrange for exit to call fini
mov.l atexit_k,r0
--- 116,127 ----
cmp/ge r0,r1
bt start_l
! #if defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
mov.l set_fpscr_k, r1
jsr @r1
mov #0,r4
lds r3,fpscr
! #endif /* defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) */
! arrange for exit to call fini
mov.l atexit_k,r0
*************** start_l:
*** 146,155 ****
nop
.align 2
! #if defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
set_fpscr_k:
.long ___set_fpscr
! #endif /* defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) */
stack_k:
.long _stack
edata_k:
--- 146,156 ----
nop
.align 2
! #if defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
set_fpscr_k:
.long ___set_fpscr
! #endif /* defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) */
!
stack_k:
.long _stack
edata_k:
Index: gcc/config/sh/lib1funcs.asm
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/lib1funcs.asm,v
retrieving revision 1.32
diff -c -3 -p -w -r1.32 lib1funcs.asm
*** gcc/config/sh/lib1funcs.asm 21 Dec 2002 23:26:16 -0000 1.32
--- gcc/config/sh/lib1funcs.asm 23 Jan 2003 18:26:19 -0000
*************** GLOBAL(sdivsi3_i4):
*** 1044,1050 ****
#ifdef L_sdivsi3
/* __SH4_SINGLE_ONLY__ keeps this part for link compatibility with
! sh3e code. */
#if (! defined(__SH4__) && ! defined (__SH4_SINGLE__)) || defined (__linux__)
!!
!! Steve Chamberlain
--- 1044,1050 ----
#ifdef L_sdivsi3
/* __SH4_SINGLE_ONLY__ keeps this part for link compatibility with
! sh2e/sh3e code. */
#if (! defined(__SH4__) && ! defined (__SH4_SINGLE__)) || defined (__linux__)
!!
!! Steve Chamberlain
*************** L1:
*** 1433,1439 ****
#ifdef L_udivsi3
/* __SH4_SINGLE_ONLY__ keeps this part for link compatibility with
! sh3e code. */
#if (! defined(__SH4__) && ! defined (__SH4_SINGLE__)) || defined (__linux__)
!! args in r4 and r5, result in r0, clobbers r4, pr, and t bit
--- 1433,1439 ----
#ifdef L_udivsi3
/* __SH4_SINGLE_ONLY__ keeps this part for link compatibility with
! sh2e/sh3e code. */
#if (! defined(__SH4__) && ! defined (__SH4_SINGLE__)) || defined (__linux__)
!! args in r4 and r5, result in r0, clobbers r4, pr, and t bit
*************** GLOBAL(moddi3):
*** 1928,1934 ****
#endif /* L_moddi3 */
#ifdef L_set_fpscr
! #if defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) || __SH5__ == 32
#ifdef __SH5__
.mode SHcompact
#endif
--- 1928,1934 ----
#endif /* L_moddi3 */
#ifdef L_set_fpscr
! #if defined (__SH2E__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) || __SH5__ == 32
#ifdef __SH5__
.mode SHcompact
#endif
*************** GLOBAL(set_fpscr):
*** 1945,1951 ****
#if defined(__SH4__)
swap.w r0,r3
mov.l r3,@(4,r1)
! #else /* defined(__SH3E__) || defined(__SH4_SINGLE*__) */
swap.w r0,r2
mov.l r2,@r1
#endif
--- 1945,1951 ----
#if defined(__SH4__)
swap.w r0,r3
mov.l r3,@(4,r1)
! #else /* defined (__SH2E__) || defined(__SH3E__) || defined(__SH4_SINGLE*__) */
swap.w r0,r2
mov.l r2,@r1
#endif
*************** GLOBAL(set_fpscr):
*** 1958,1964 ****
swap.w r0,r2
rts
mov.l r2,@r1
! #else /* defined(__SH3E__) || defined(__SH4_SINGLE*__) */
swap.w r0,r3
rts
mov.l r3,@(4,r1)
--- 1958,1964 ----
swap.w r0,r2
rts
mov.l r2,@r1
! #else /* defined(__SH2E__) || defined(__SH3E__) || defined(__SH4_SINGLE*__) */
swap.w r0,r3
rts
mov.l r3,@(4,r1)
*************** LOCAL(set_fpscr_L1):
*** 1975,1981 ****
.comm GLOBAL(fpscr_values),8
#endif /* ELF */
#endif /* NO_FPSCR_VALUES */
! #endif /* SH3E / SH4 */
#endif /* L_set_fpscr */
#ifdef L_ic_invalidate
#if __SH5__ == 32
--- 1975,1981 ----
.comm GLOBAL(fpscr_values),8
#endif /* ELF */
#endif /* NO_FPSCR_VALUES */
! #endif /* SH2E / SH3E / SH4 */
#endif /* L_set_fpscr */
#ifdef L_ic_invalidate
#if __SH5__ == 32
Index: gcc/config/sh/sh.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.c,v
retrieving revision 1.191
diff -c -3 -p -w -r1.191 sh.c
*** gcc/config/sh/sh.c 17 Jan 2003 00:26:53 -0000 1.191
--- gcc/config/sh/sh.c 23 Jan 2003 18:26:27 -0000
*************** prepare_scc_operands (code)
*** 794,800 ****
&& (sh_compare_op1 != const0_rtx
|| code == GTU || code == GEU || code == LTU || code == LEU))
|| (mode == DImode && sh_compare_op1 != const0_rtx)
! || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
sh_compare_op1 = force_reg (mode, sh_compare_op1);
if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
--- 794,800 ----
&& (sh_compare_op1 != const0_rtx
|| code == GTU || code == GEU || code == LTU || code == LEU))
|| (mode == DImode && sh_compare_op1 != const0_rtx)
! || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
sh_compare_op1 = force_reg (mode, sh_compare_op1);
if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
*************** from_compare (operands, code)
*** 825,840 ****
mode = GET_MODE (sh_compare_op1);
if (code != EQ
|| mode == DImode
! || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
{
/* Force args into regs, since we can't use constants here. */
sh_compare_op0 = force_reg (mode, sh_compare_op0);
if (sh_compare_op1 != const0_rtx
|| code == GTU || code == GEU
! || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
sh_compare_op1 = force_reg (mode, sh_compare_op1);
}
! if (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
{
from_compare (operands, GT);
insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
--- 825,840 ----
mode = GET_MODE (sh_compare_op1);
if (code != EQ
|| mode == DImode
! || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
{
/* Force args into regs, since we can't use constants here. */
sh_compare_op0 = force_reg (mode, sh_compare_op0);
if (sh_compare_op1 != const0_rtx
|| code == GTU || code == GEU
! || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
sh_compare_op1 = force_reg (mode, sh_compare_op1);
}
! if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
{
from_compare (operands, GT);
insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
*************** output_branch (logic, insn, operands)
*** 1091,1096 ****
--- 1091,1129 ----
will fix it up if it still doesn't fit after relaxation. */
case 2:
return logic ? "bt%.\t%l0" : "bf%.\t%l0";
+
+ /* These are for SH2e, in which we have to account for the
+ extra nop because of the hardware bug in annulled branches. */
+ case 8:
+ if (! TARGET_RELAX)
+ {
+ int label = lf++;
+
+ if (final_sequence
+ && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
+ abort ();
+ asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
+ logic ? "f" : "t",
+ ASSEMBLER_DIALECT ? "/" : ".", label);
+ fprintf (asm_out_file, "\tnop\n");
+ output_asm_insn ("bra\t%l0", operands);
+ fprintf (asm_out_file, "\tnop\n");
+ (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
+
+ return "";
+ }
+ /* When relaxing, fall through. */
+ case 4:
+ {
+ char buffer[10];
+
+ sprintf (buffer, "b%s%ss\t%%l0",
+ logic ? "t" : "f",
+ ASSEMBLER_DIALECT ? "/" : ".");
+ output_asm_insn (buffer, &operands[0]);
+ return "nop";
+ }
+
default:
/* There should be no longer branches now - that would
indicate that something has destroyed the branches set
*************** broken_move (insn)
*** 2559,2565 ****
|| (GET_CODE (SET_SRC (pat)) == UNSPEC
&& XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
&& GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
! && ! (TARGET_SH3E
&& GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
&& (fp_zero_operand (SET_SRC (pat))
|| fp_one_operand (SET_SRC (pat)))
--- 2592,2598 ----
|| (GET_CODE (SET_SRC (pat)) == UNSPEC
&& XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
&& GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
! && ! (TARGET_SH2E
&& GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
&& (fp_zero_operand (SET_SRC (pat))
|| fp_one_operand (SET_SRC (pat)))
*************** push (rn)
*** 4321,4327 ****
return NULL_RTX;
x = gen_push_4 (gen_rtx_REG (DFmode, rn));
}
! else if (TARGET_SH3E && FP_REGISTER_P (rn))
x = gen_push_e (gen_rtx_REG (SFmode, rn));
else
x = gen_push (gen_rtx_REG (SImode, rn));
--- 4354,4360 ----
return NULL_RTX;
x = gen_push_4 (gen_rtx_REG (DFmode, rn));
}
! else if (TARGET_SH2E && FP_REGISTER_P (rn))
x = gen_push_e (gen_rtx_REG (SFmode, rn));
else
x = gen_push (gen_rtx_REG (SImode, rn));
*************** pop (rn)
*** 4351,4357 ****
return;
x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
}
! else if (TARGET_SH3E && FP_REGISTER_P (rn))
x = gen_pop_e (gen_rtx_REG (SFmode, rn));
else
x = gen_pop (gen_rtx_REG (SImode, rn));
--- 4384,4390 ----
return;
x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
}
! else if (TARGET_SH2E && FP_REGISTER_P (rn))
x = gen_pop_e (gen_rtx_REG (SFmode, rn));
else
x = gen_pop (gen_rtx_REG (SImode, rn));
*************** sh_expand_prologue ()
*** 4590,4597 ****
/* Emit the code for SETUP_VARARGS. */
if (current_function_stdarg)
{
! /* This is not used by the SH3E calling convention */
! if (TARGET_SH1 && ! TARGET_SH3E && ! TARGET_SH5 && ! TARGET_HITACHI)
{
/* Push arg regs as if they'd been provided by caller in stack. */
for (i = 0; i < NPARM_REGS(SImode); i++)
--- 4623,4630 ----
/* Emit the code for SETUP_VARARGS. */
if (current_function_stdarg)
{
! /* This is not used by the SH2E calling convention */
! if (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 && ! TARGET_HITACHI)
{
/* Push arg regs as if they'd been provided by caller in stack. */
for (i = 0; i < NPARM_REGS(SImode); i++)
*************** sh_builtin_saveregs ()
*** 5246,5252 ****
return const0_rtx;
}
! if (! TARGET_SH3E && ! TARGET_SH4 && ! TARGET_SH5)
{
error ("__builtin_saveregs not supported by this subtarget");
return const0_rtx;
--- 5279,5285 ----
return const0_rtx;
}
! if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5)
{
error ("__builtin_saveregs not supported by this subtarget");
return const0_rtx;
*************** sh_build_va_list ()
*** 5349,5355 ****
tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
tree record;
! if (TARGET_SH5 || (! TARGET_SH3E && ! TARGET_SH4) || TARGET_HITACHI)
return ptr_type_node;
record = make_node (RECORD_TYPE);
--- 5382,5388 ----
tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
tree record;
! if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4) || TARGET_HITACHI)
return ptr_type_node;
record = make_node (RECORD_TYPE);
*************** sh_va_start (valist, nextarg)
*** 5403,5409 ****
return;
}
! if ((! TARGET_SH3E && ! TARGET_SH4) || TARGET_HITACHI)
{
std_expand_builtin_va_start (valist, nextarg);
return;
--- 5436,5442 ----
return;
}
! if ((! TARGET_SH2E && ! TARGET_SH4) || TARGET_HITACHI)
{
std_expand_builtin_va_start (valist, nextarg);
return;
*************** sh_va_arg (valist, type)
*** 5481,5487 ****
if (pass_by_ref)
type = build_pointer_type (type);
! if (! TARGET_SH5 && (TARGET_SH3E || TARGET_SH4) && ! TARGET_HITACHI)
{
tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
--- 5514,5520 ----
if (pass_by_ref)
type = build_pointer_type (type);
! if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4) && ! TARGET_HITACHI)
{
tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
*************** sh_insn_length_adjustment (insn)
*** 6875,6880 ****
--- 6908,6923 ----
&& GET_CODE (PATTERN (insn)) != ADDR_VEC))
&& GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
&& get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
+ return 2;
+
+ /* SH2e has a bug that prevents the use of annulled branches, so if
+ the delay slot is not filled, we'll have to put a NOP in it. */
+ if (sh_cpu == CPU_SH2E
+ && GET_CODE (insn) == JUMP_INSN
+ && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
+ && GET_CODE (PATTERN (insn)) != ADDR_VEC
+ && get_attr_type (insn) == TYPE_CBRANCH
+ && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE)
return 2;
/* sh-dsp parallel processing insn take four bytes instead of two. */
Index: gcc/config/sh/sh.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.h,v
retrieving revision 1.184
diff -c -3 -p -w -r1.184 sh.h
*** gcc/config/sh/sh.h 9 Jan 2003 17:25:29 -0000 1.184
--- gcc/config/sh/sh.h 23 Jan 2003 18:26:32 -0000
*************** do { \
*** 45,50 ****
--- 45,53 ----
case PROCESSOR_SH2: \
builtin_define ("__sh2__"); \
break; \
+ case PROCESSOR_SH2E: \
+ builtin_define ("__SH2E__"); \
+ break; \
case PROCESSOR_SH3: \
builtin_define ("__sh3__"); \
builtin_define ("__SH3__"); \
*************** extern int target_flags;
*** 132,138 ****
#define SH1_BIT (1<<8)
#define SH2_BIT (1<<9)
#define SH3_BIT (1<<10)
! #define SH3E_BIT (1<<11)
#define HARD_SH4_BIT (1<<5)
#define FPU_SINGLE_BIT (1<<7)
#define SH4_BIT (1<<12)
--- 135,141 ----
#define SH1_BIT (1<<8)
#define SH2_BIT (1<<9)
#define SH3_BIT (1<<10)
! #define SH_E_BIT (1<<11)
#define HARD_SH4_BIT (1<<5)
#define FPU_SINGLE_BIT (1<<7)
#define SH4_BIT (1<<12)
*************** extern int target_flags;
*** 161,171 ****
/* Nonzero if we should generate code using type 2 insns. */
#define TARGET_SH2 (target_flags & SH2_BIT)
/* Nonzero if we should generate code using type 3 insns. */
#define TARGET_SH3 (target_flags & SH3_BIT)
/* Nonzero if we should generate code using type 3E insns. */
! #define TARGET_SH3E ((target_flags & SH3E_BIT) && (target_flags & SH1_BIT))
/* Nonzero if the cache line size is 32. */
#define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
--- 164,177 ----
/* Nonzero if we should generate code using type 2 insns. */
#define TARGET_SH2 (target_flags & SH2_BIT)
+ /* Nonzero if we should generate code using type 2E insns. */
+ #define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
+
/* Nonzero if we should generate code using type 3 insns. */
#define TARGET_SH3 (target_flags & SH3_BIT)
/* Nonzero if we should generate code using type 3E insns. */
! #define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
/* Nonzero if the cache line size is 32. */
#define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
*************** extern int target_flags;
*** 186,192 ****
#define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
/* Nonzero if an FPU is available. */
! #define TARGET_FPU_ANY (TARGET_SH3E || TARGET_FPU_DOUBLE)
/* Nonzero if we should generate code using type 4 insns. */
#define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
--- 192,198 ----
#define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
/* Nonzero if an FPU is available. */
! #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
/* Nonzero if we should generate code using type 4 insns. */
#define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
*************** extern int target_flags;
*** 205,216 ****
/* Nonzero if we should generate code using the SHmedia ISA and 32-bit
ABI. */
#define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
! && (target_flags & SH3E_BIT))
/* Nonzero if we should generate code using the SHmedia ISA and 64-bit
ABI. */
#define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
! && ! (target_flags & SH3E_BIT))
/* Nonzero if we should generate code using SHmedia FPU instructions. */
#define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
--- 211,222 ----
/* Nonzero if we should generate code using the SHmedia ISA and 32-bit
ABI. */
#define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
! && (target_flags & SH_E_BIT))
/* Nonzero if we should generate code using the SHmedia ISA and 64-bit
ABI. */
#define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
! && ! (target_flags & SH_E_BIT))
/* Nonzero if we should generate code using SHmedia FPU instructions. */
#define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
*************** extern int target_flags;
*** 254,274 ****
#define SELECT_SH1 (SH1_BIT)
#define SELECT_SH2 (SH2_BIT | SELECT_SH1)
#define SELECT_SH3 (SH3_BIT | SELECT_SH2)
! #define SELECT_SH3E (SH3E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
#define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
#define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
! #define SELECT_SH4 (SH4_BIT|SH3E_BIT|HARD_SH4_BIT | SELECT_SH3)
#define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
#define SELECT_SH5_64 (SH5_BIT | SH4_BIT)
#define SELECT_SH5_64_NOFPU (SH5_BIT)
! #define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH3E_BIT)
! #define SELECT_SH5_32_NOFPU (SH5_BIT | SH3E_BIT)
#define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
#define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
/* Reset all target-selection flags. */
! #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH3E_BIT | SH4_BIT \
| HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
#define TARGET_SWITCHES \
--- 260,281 ----
#define SELECT_SH1 (SH1_BIT)
#define SELECT_SH2 (SH2_BIT | SELECT_SH1)
+ #define SELECT_SH2E (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
#define SELECT_SH3 (SH3_BIT | SELECT_SH2)
! #define SELECT_SH3E (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
#define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
#define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
! #define SELECT_SH4 (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
#define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
#define SELECT_SH5_64 (SH5_BIT | SH4_BIT)
#define SELECT_SH5_64_NOFPU (SH5_BIT)
! #define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH_E_BIT)
! #define SELECT_SH5_32_NOFPU (SH5_BIT | SH_E_BIT)
#define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
#define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
/* Reset all target-selection flags. */
! #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
| HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
#define TARGET_SWITCHES \
*************** extern int target_flags;
*** 276,281 ****
--- 283,290 ----
{"1", SELECT_SH1, "" }, \
{"2", TARGET_NONE, "" }, \
{"2", SELECT_SH2, "" }, \
+ {"2e", TARGET_NONE, "" }, \
+ {"2e", SELECT_SH2E, "" }, \
{"3", TARGET_NONE, "" }, \
{"3", SELECT_SH3, "" }, \
{"3e", TARGET_NONE, "" }, \
*************** extern int target_flags;
*** 365,375 ****
#define LINK_EMUL_PREFIX "sh%{ml:l}"
#if TARGET_CPU_DEFAULT & SH5_BIT
! #if TARGET_CPU_DEFAULT & SH3E_BIT
#define LINK_DEFAULT_CPU_EMUL "32"
#else
#define LINK_DEFAULT_CPU_EMUL "64"
! #endif /* SH3E_BIT */
#else
#define LINK_DEFAULT_CPU_EMUL ""
#endif /* SH5_BIT */
--- 374,384 ----
#define LINK_EMUL_PREFIX "sh%{ml:l}"
#if TARGET_CPU_DEFAULT & SH5_BIT
! #if TARGET_CPU_DEFAULT & SH_E_BIT
#define LINK_DEFAULT_CPU_EMUL "32"
#else
#define LINK_DEFAULT_CPU_EMUL "64"
! #endif /* SH_E_BIT */
#else
#define LINK_DEFAULT_CPU_EMUL ""
#endif /* SH5_BIT */
*************** do { \
*** 409,414 ****
--- 418,425 ----
assembler_dialect = 0; \
if (TARGET_SH2) \
sh_cpu = CPU_SH2; \
+ if (TARGET_SH2E) \
+ sh_cpu = CPU_SH2E; \
if (TARGET_SH3) \
sh_cpu = CPU_SH3; \
if (TARGET_SH3E) \
*************** extern char sh_additional_register_names
*** 737,743 ****
#define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
#define FIRST_FP_REG DR0_REG
#define LAST_FP_REG (FIRST_FP_REG + \
! (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH3E ? 15 : -1))
#define FIRST_XD_REG XD0_REG
#define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
#define FIRST_TARGET_REG TR0_REG
--- 748,754 ----
#define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
#define FIRST_FP_REG DR0_REG
#define LAST_FP_REG (FIRST_FP_REG + \
! (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
#define FIRST_XD_REG XD0_REG
#define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
#define FIRST_TARGET_REG TR0_REG
*************** extern char sh_additional_register_names
*** 778,784 ****
(SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
|| (REGNO) == AP_REG || (REGNO) == RAP_REG \
|| (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
! || (TARGET_SH3E && (REGNO) == FPUL_REG))
/* The mode that should be generally used to store a register by
itself in the stack, or to load it back. */
--- 789,795 ----
(SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
|| (REGNO) == AP_REG || (REGNO) == RAP_REG \
|| (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
! || (TARGET_SH2E && (REGNO) == FPUL_REG))
/* The mode that should be generally used to store a register by
itself in the stack, or to load it back. */
*************** extern char sh_additional_register_names
*** 927,933 ****
: (REGNO) == FIRST_XD_REG) \
: FP_REGISTER_P (REGNO) \
? ((MODE) == SFmode || (MODE) == SImode \
! || ((TARGET_SH3E || TARGET_SHMEDIA) && (MODE) == SCmode) \
|| (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
|| (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
|| (MODE) == V2SFmode || (MODE) == TImode))) \
--- 938,944 ----
: (REGNO) == FIRST_XD_REG) \
: FP_REGISTER_P (REGNO) \
? ((MODE) == SFmode || (MODE) == SImode \
! || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
|| (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
|| (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
|| (MODE) == V2SFmode || (MODE) == TImode))) \
*************** extern enum reg_class reg_class_from_let
*** 1468,1474 ****
: FIRST_RET_REG)
#define BASE_ARG_REG(MODE) \
! ((TARGET_SH3E && ((MODE) == SFmode)) \
? FIRST_FP_PARM_REG \
: TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
--- 1479,1485 ----
: FIRST_RET_REG)
#define BASE_ARG_REG(MODE) \
! ((TARGET_SH2E && ((MODE) == SFmode)) \
? FIRST_FP_PARM_REG \
: TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
*************** extern enum reg_class reg_class_from_let
*** 1504,1510 ****
/* 1 if N is a possible register number for a function value. */
#define FUNCTION_VALUE_REGNO_P(REGNO) \
! ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG) \
|| (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
/* 1 if N is a possible register number for function argument passing. */
--- 1515,1521 ----
/* 1 if N is a possible register number for a function value. */
#define FUNCTION_VALUE_REGNO_P(REGNO) \
! ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
|| (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
/* 1 if N is a possible register number for function argument passing. */
*************** struct sh_args {
*** 1838,1844 ****
|| (! TREE_ADDRESSABLE ((tree)(TYPE)) \
&& (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
&& ! (CUM).force_mem \
! && (TARGET_SH3E \
? ((MODE) == BLKmode \
? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
+ int_size_in_bytes (TYPE)) \
--- 1849,1855 ----
|| (! TREE_ADDRESSABLE ((tree)(TYPE)) \
&& (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
&& ! (CUM).force_mem \
! && (TARGET_SH2E \
? ((MODE) == BLKmode \
? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
+ int_size_in_bytes (TYPE)) \
*************** while (0)
*** 2181,2187 ****
|| TARGET_SHMEDIA64) \
: (GET_CODE (X) != CONST_DOUBLE \
|| GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
! || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X)))))
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
--- 2192,2198 ----
|| TARGET_SHMEDIA64) \
: (GET_CODE (X) != CONST_DOUBLE \
|| GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
! || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
*************** while (0)
*** 2336,2342 ****
#define MODE_DISP_OK_4(X,MODE) \
(GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
! && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode))
#define MODE_DISP_OK_8(X,MODE) \
((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
--- 2347,2353 ----
#define MODE_DISP_OK_4(X,MODE) \
(GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
! && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
#define MODE_DISP_OK_8(X,MODE) \
((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
*************** while (0)
*** 2367,2373 ****
REG++
--REG */
! /* ??? The SH3e does not have the REG+disp addressing mode when loading values
into the FRx registers. We implement this by setting the maximum offset
to zero when the value is SFmode. This also restricts loading of SFmode
values into the integer registers, but that can't be helped. */
--- 2378,2384 ----
REG++
--REG */
! /* ??? The SH2e does not have the REG+disp addressing mode when loading values
into the FRx registers. We implement this by setting the maximum offset
to zero when the value is SFmode. This also restricts loading of SFmode
values into the integer registers, but that can't be helped. */
*************** while (0)
*** 2453,2459 ****
&& BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
&& ! TARGET_SHMEDIA \
&& ! (TARGET_SH4 && (MODE) == DFmode) \
! && ! (TARGET_SH3E && (MODE) == SFmode)) \
{ \
rtx index_rtx = XEXP ((X), 1); \
HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
--- 2464,2470 ----
&& BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
&& ! TARGET_SHMEDIA \
&& ! (TARGET_SH4 && (MODE) == DFmode) \
! && ! (TARGET_SH2E && (MODE) == SFmode)) \
{ \
rtx index_rtx = XEXP ((X), 1); \
HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
*************** while (0)
*** 2508,2514 ****
HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
rtx sum; \
\
! if (TARGET_SH3E && MODE == SFmode) \
{ \
X = copy_rtx (X); \
push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
--- 2519,2525 ----
HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
rtx sum; \
\
! if (TARGET_SH2E && MODE == SFmode) \
{ \
X = copy_rtx (X); \
push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
*************** while (0)
*** 2547,2553 ****
&& BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
&& ! TARGET_SHMEDIA \
! && ! (TARGET_SH3E && MODE == SFmode)) \
{ \
/* Because this address is so complex, we know it must have \
been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
--- 2558,2564 ----
&& BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
&& ! TARGET_SHMEDIA \
! && ! (TARGET_SH2E && MODE == SFmode)) \
{ \
/* Because this address is so complex, we know it must have \
been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
*************** while (0)
*** 2593,2601 ****
/* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
#define FLOAT_TYPE_SIZE 32
! /* Since the SH3e has only `float' support, it is desirable to make all
floating point types equivalent to `float'. */
! #define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64)
/* 'char' is signed by default. */
#define DEFAULT_SIGNED_CHAR 1
--- 2604,2612 ----
/* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
#define FLOAT_TYPE_SIZE 32
! /* Since the SH2e has only `float' support, it is desirable to make all
floating point types equivalent to `float'. */
! #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4) ? 32 : 64)
/* 'char' is signed by default. */
#define DEFAULT_SIGNED_CHAR 1
*************** extern struct rtx_def *sh_compare_op1;
*** 3138,3143 ****
--- 3149,3155 ----
enum processor_type {
PROCESSOR_SH1,
PROCESSOR_SH2,
+ PROCESSOR_SH2E,
PROCESSOR_SH3,
PROCESSOR_SH3E,
PROCESSOR_SH4,
*************** extern int rtx_equal_function_value_matt
*** 3286,3292 ****
: TARGET_FPU_SINGLE ? FP_MODE_SINGLE \
: FP_MODE_DOUBLE)
! #define EPILOGUE_USES(REGNO) ((TARGET_SH3E || TARGET_SH4) \
&& (REGNO) == FPSCR_REG)
#define MODE_NEEDED(ENTITY, INSN) \
--- 3298,3304 ----
: TARGET_FPU_SINGLE ? FP_MODE_SINGLE \
: FP_MODE_DOUBLE)
! #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
&& (REGNO) == FPSCR_REG)
#define MODE_NEEDED(ENTITY, INSN) \
Index: gcc/config/sh/sh.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.md,v
retrieving revision 1.136
diff -c -3 -p -w -r1.136 sh.md
*** gcc/config/sh/sh.md 16 Jan 2003 21:43:43 -0000 1.136
--- gcc/config/sh/sh.md 23 Jan 2003 18:26:39 -0000
***************
*** 154,160 ****
;; Target CPU.
(define_attr "cpu"
! "sh1,sh2,sh3,sh3e,sh4,sh5"
(const (symbol_ref "sh_cpu_attr")))
(define_attr "endian" "big,little"
--- 154,160 ----
;; Target CPU.
(define_attr "cpu"
! "sh1,sh2,sh2e,sh3,sh3e,sh4,sh5"
(const (symbol_ref "sh_cpu_attr")))
(define_attr "endian" "big,little"
***************
*** 609,615 ****
(define_delay
(and (eq_attr "type" "cbranch")
(ne (symbol_ref "TARGET_SH2") (const_int 0)))
! [(eq_attr "in_delay_slot" "yes") (eq_attr "cond_delay_slot" "yes") (nil)])
;; -------------------------------------------------------------------------
;; SImode signed integer comparisons
--- 609,618 ----
(define_delay
(and (eq_attr "type" "cbranch")
(ne (symbol_ref "TARGET_SH2") (const_int 0)))
! ;; SH2e has a hardware bug that pretty much prohibits the use of
! ;; annuled delay slots.
! [(eq_attr "in_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
! (not (eq_attr "cpu" "sh2e"))) (nil)])
;; -------------------------------------------------------------------------
;; SImode signed integer comparisons
***************
*** 1346,1352 ****
operands[3] = gen_reg_rtx (Pmode);
/* Emit the move of the address to a pseudo outside of the libcall. */
! if (TARGET_HARD_SH4 && TARGET_SH3E)
{
emit_move_insn (operands[3],
gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
--- 1349,1355 ----
operands[3] = gen_reg_rtx (Pmode);
/* Emit the move of the address to a pseudo outside of the libcall. */
! if (TARGET_HARD_SH4 && TARGET_SH2E)
{
emit_move_insn (operands[3],
gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
***************
*** 1496,1502 ****
operands[3] = gen_reg_rtx (Pmode);
/* Emit the move of the address to a pseudo outside of the libcall. */
! if (TARGET_HARD_SH4 && TARGET_SH3E)
{
emit_move_insn (operands[3],
gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
--- 1499,1505 ----
operands[3] = gen_reg_rtx (Pmode);
/* Emit the move of the address to a pseudo outside of the libcall. */
! if (TARGET_HARD_SH4 && TARGET_SH2E)
{
emit_move_insn (operands[3],
gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
***************
*** 3297,3303 ****
(define_insn "push_fpul"
[(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
! "TARGET_SH3E && ! TARGET_SH5"
"sts.l fpul,@-r15"
[(set_attr "type" "store")
(set_attr "late_fp_use" "yes")
--- 3300,3306 ----
(define_insn "push_fpul"
[(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
! "TARGET_SH2E && ! TARGET_SH5"
"sts.l fpul,@-r15"
[(set_attr "type" "store")
(set_attr "late_fp_use" "yes")
***************
*** 3323,3329 ****
(define_insn "pop_fpul"
[(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
! "TARGET_SH3E && ! TARGET_SH5"
"lds.l @r15+,fpul"
[(set_attr "type" "load")
(set_attr "hit_stack" "yes")])
--- 3326,3332 ----
(define_insn "pop_fpul"
[(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
! "TARGET_SH2E && ! TARGET_SH5"
"lds.l @r15+,fpul"
[(set_attr "type" "load")
(set_attr "hit_stack" "yes")])
***************
*** 3383,3389 ****
[(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
(match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
"TARGET_SH1
! && ! TARGET_SH3E
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
"@
--- 3386,3392 ----
[(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
(match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
"TARGET_SH1
! && ! TARGET_SH2E
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
"@
***************
*** 3414,3420 ****
(define_insn "movsi_ie"
[(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
(match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
! "TARGET_SH3E
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
"@
--- 3417,3423 ----
(define_insn "movsi_ie"
[(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
(match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
! "TARGET_SH2E
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
"@
***************
*** 4354,4360 ****
(match_operand:SF 1 "register_operand" ""))
(use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (match_scratch:SI 3 "X"))]
! "TARGET_SH3E && reload_completed
&& true_regnum (operands[0]) == true_regnum (operands[1])"
[(set (match_dup 0) (match_dup 0))]
"")
--- 4357,4363 ----
(match_operand:SF 1 "register_operand" ""))
(use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (match_scratch:SI 3 "X"))]
! "TARGET_SH2E && reload_completed
&& true_regnum (operands[0]) == true_regnum (operands[1])"
[(set (match_dup 0) (match_dup 0))]
"")
***************
*** 4843,4849 ****
[(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
(match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
"TARGET_SH1
! && (! TARGET_SH3E
/* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
|| (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
|| (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
--- 4846,4852 ----
[(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
(match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
"TARGET_SH1
! && (! TARGET_SH2E
/* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
|| (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
|| (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
***************
*** 4870,4876 ****
(use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
(clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
! "TARGET_SH3E
&& (arith_reg_operand (operands[0], SFmode)
|| arith_reg_operand (operands[1], SFmode)
|| arith_reg_operand (operands[3], SImode)
--- 4873,4879 ----
(use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
(clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
! "TARGET_SH2E
&& (arith_reg_operand (operands[0], SFmode)
|| arith_reg_operand (operands[1], SFmode)
|| arith_reg_operand (operands[3], SImode)
***************
*** 4937,4943 ****
emit_insn (gen_movsf_media_nofpu (operands[0], operands[1]));
DONE;
}
! if (TARGET_SH3E)
{
emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
DONE;
--- 4940,4946 ----
emit_insn (gen_movsf_media_nofpu (operands[0], operands[1]));
DONE;
}
! if (TARGET_SH2E)
{
emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
DONE;
***************
*** 4946,4952 ****
(define_insn "mov_nop"
[(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
! "TARGET_SH3E"
""
[(set_attr "length" "0")
(set_attr "type" "nil")])
--- 4949,4955 ----
(define_insn "mov_nop"
[(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
! "TARGET_SH2E"
""
[(set_attr "length" "0")
(set_attr "type" "nil")])
***************
*** 4970,4976 ****
[(set (match_operand:SI 0 "register_operand" "=y,y")
(match_operand:SI 1 "immediate_operand" "Qi,I"))
(clobber (match_scratch:SI 2 "=&z,r"))]
! "TARGET_SH3E
&& (reload_in_progress || reload_completed)"
"#"
[(set_attr "length" "4")
--- 4973,4979 ----
[(set (match_operand:SI 0 "register_operand" "=y,y")
(match_operand:SI 1 "immediate_operand" "Qi,I"))
(clobber (match_scratch:SI 2 "=&z,r"))]
! "TARGET_SH2E
&& (reload_in_progress || reload_completed)"
"#"
[(set_attr "length" "4")
***************
*** 5290,5296 ****
DONE;
}
! if (TARGET_SH3E
&& TARGET_IEEE
&& GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
{
--- 5293,5299 ----
DONE;
}
! if (TARGET_SH2E
&& TARGET_IEEE
&& GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
{
***************
*** 5331,5337 ****
DONE;
}
! if (TARGET_SH3E
&& ! TARGET_IEEE
&& GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
{
--- 5334,5340 ----
DONE;
}
! if (TARGET_SH2E
&& ! TARGET_IEEE
&& GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
{
***************
*** 6487,6493 ****
(const_int 0))
(match_operand 1 "" "")
(match_operand 2 "" "")])]
! "TARGET_SH3E || TARGET_SHMEDIA"
"
{
int i;
--- 6490,6496 ----
(const_int 0))
(match_operand 1 "" "")
(match_operand 2 "" "")])]
! "TARGET_SH2E || TARGET_SHMEDIA"
"
{
int i;
***************
*** 7991,8000 ****
[(set (match_operand:SF 0 "arith_reg_operand" "")
(plus:SF (match_operand:SF 1 "arith_reg_operand" "")
(match_operand:SF 2 "arith_reg_operand" "")))]
! "TARGET_SH3E || TARGET_SHMEDIA_FPU"
"
{
! if (TARGET_SH3E)
{
expand_sf_binop (&gen_addsf3_i, operands);
DONE;
--- 7994,8003 ----
[(set (match_operand:SF 0 "arith_reg_operand" "")
(plus:SF (match_operand:SF 1 "arith_reg_operand" "")
(match_operand:SF 2 "arith_reg_operand" "")))]
! "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
! if (TARGET_SH2E)
{
expand_sf_binop (&gen_addsf3_i, operands);
DONE;
***************
*** 8080,8086 ****
(plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
(match_operand:SF 2 "arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
! "TARGET_SH3E"
"fadd %2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
--- 8083,8089 ----
(plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
(match_operand:SF 2 "arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
! "TARGET_SH2E"
"fadd %2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
***************
*** 8089,8098 ****
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
(match_operand:SF 2 "fp_arith_reg_operand" "")))]
! "TARGET_SH3E || TARGET_SHMEDIA_FPU"
"
{
! if (TARGET_SH3E)
{
expand_sf_binop (&gen_subsf3_i, operands);
DONE;
--- 8092,8101 ----
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
(match_operand:SF 2 "fp_arith_reg_operand" "")))]
! "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
! if (TARGET_SH2E)
{
expand_sf_binop (&gen_subsf3_i, operands);
DONE;
***************
*** 8112,8118 ****
(minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
! "TARGET_SH3E"
"fsub %2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
--- 8115,8121 ----
(minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
! "TARGET_SH2E"
"fsub %2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
***************
*** 8126,8137 ****
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
(match_operand:SF 2 "fp_arith_reg_operand" "")))]
! "TARGET_SH3E || TARGET_SHMEDIA_FPU"
"
{
if (TARGET_SH4)
expand_sf_binop (&gen_mulsf3_i4, operands);
! else if (TARGET_SH3E)
emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
if (! TARGET_SHMEDIA)
DONE;
--- 8129,8140 ----
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
(match_operand:SF 2 "fp_arith_reg_operand" "")))]
! "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
if (TARGET_SH4)
expand_sf_binop (&gen_mulsf3_i4, operands);
! else if (TARGET_SH2E)
emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
if (! TARGET_SHMEDIA)
DONE;
***************
*** 8150,8156 ****
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
! "TARGET_SH3E"
"fmul %2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
--- 8153,8159 ----
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
! "TARGET_SH2E"
"fmul %2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
***************
*** 8159,8165 ****
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))]
! "TARGET_SH3E && ! TARGET_SH4"
"fmul %2,%0"
[(set_attr "type" "fp")])
--- 8162,8168 ----
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))]
! "TARGET_SH2E && ! TARGET_SH4"
"fmul %2,%0"
[(set_attr "type" "fp")])
***************
*** 8178,8184 ****
(match_operand:SF 2 "fp_arith_reg_operand" "f"))
(match_operand:SF 3 "arith_reg_operand" "0")))
(use (match_operand:PSI 4 "fpscr_operand" "c"))]
! "TARGET_SH3E && ! TARGET_SH4"
"fmac fr0,%2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
--- 8181,8187 ----
(match_operand:SF 2 "fp_arith_reg_operand" "f"))
(match_operand:SF 3 "arith_reg_operand" "0")))
(use (match_operand:PSI 4 "fpscr_operand" "c"))]
! "TARGET_SH2E && ! TARGET_SH4"
"fmac fr0,%2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
***************
*** 8187,8196 ****
[(set (match_operand:SF 0 "arith_reg_operand" "")
(div:SF (match_operand:SF 1 "arith_reg_operand" "")
(match_operand:SF 2 "arith_reg_operand" "")))]
! "TARGET_SH3E || TARGET_SHMEDIA_FPU"
"
{
! if (TARGET_SH3E)
{
expand_sf_binop (&gen_divsf3_i, operands);
DONE;
--- 8190,8199 ----
[(set (match_operand:SF 0 "arith_reg_operand" "")
(div:SF (match_operand:SF 1 "arith_reg_operand" "")
(match_operand:SF 2 "arith_reg_operand" "")))]
! "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
! if (TARGET_SH2E)
{
expand_sf_binop (&gen_divsf3_i, operands);
DONE;
***************
*** 8210,8216 ****
(div:SF (match_operand:SF 1 "arith_reg_operand" "0")
(match_operand:SF 2 "arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
! "TARGET_SH3E"
"fdiv %2,%0"
[(set_attr "type" "fdiv")
(set_attr "fp_mode" "single")])
--- 8213,8219 ----
(div:SF (match_operand:SF 1 "arith_reg_operand" "0")
(match_operand:SF 2 "arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
! "TARGET_SH2E"
"fdiv %2,%0"
[(set_attr "type" "fdiv")
(set_attr "fp_mode" "single")])
***************
*** 8225,8231 ****
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(float:SF (match_operand:SI 1 "fpul_operand" "")))]
! "TARGET_SH3E || TARGET_SHMEDIA_FPU"
"
{
if (TARGET_SH4)
--- 8228,8234 ----
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(float:SF (match_operand:SI 1 "fpul_operand" "")))]
! "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
if (TARGET_SH4)
***************
*** 8254,8260 ****
(define_insn "*floatsisf2_ie"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(float:SF (match_operand:SI 1 "fpul_operand" "y")))]
! "TARGET_SH3E && ! TARGET_SH4"
"float %1,%0"
[(set_attr "type" "fp")])
--- 8257,8263 ----
(define_insn "*floatsisf2_ie"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(float:SF (match_operand:SI 1 "fpul_operand" "y")))]
! "TARGET_SH2E && ! TARGET_SH4"
"float %1,%0"
[(set_attr "type" "fp")])
***************
*** 8268,8274 ****
(define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "fpul_operand" "=y")
(fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
! "TARGET_SH3E || TARGET_SHMEDIA_FPU"
"
{
if (TARGET_SH4)
--- 8271,8277 ----
(define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "fpul_operand" "=y")
(fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
! "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
if (TARGET_SH4)
***************
*** 8319,8325 ****
(define_insn "*fixsfsi"
[(set (match_operand:SI 0 "fpul_operand" "=y")
(fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
! "TARGET_SH3E && ! TARGET_SH4"
"ftrc %1,%0"
[(set_attr "type" "fp")])
--- 8322,8328 ----
(define_insn "*fixsfsi"
[(set (match_operand:SI 0 "fpul_operand" "=y")
(fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
! "TARGET_SH2E && ! TARGET_SH4"
"ftrc %1,%0"
[(set_attr "type" "fp")])
***************
*** 8327,8333 ****
[(set (reg:SI T_REG)
(gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f")))]
! "TARGET_SH3E && ! TARGET_SH4"
"fcmp/gt %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
--- 8330,8336 ----
[(set (reg:SI T_REG)
(gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f")))]
! "TARGET_SH2E && ! TARGET_SH4"
"fcmp/gt %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
***************
*** 8336,8342 ****
[(set (reg:SI T_REG)
(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f")))]
! "TARGET_SH3E && ! TARGET_SH4"
"fcmp/eq %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
--- 8339,8345 ----
[(set (reg:SI T_REG)
(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f")))]
! "TARGET_SH2E && ! TARGET_SH4"
"fcmp/eq %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
***************
*** 8346,8352 ****
(ior:SI (reg:SI T_REG)
(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
! "TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
"* return output_ieee_ccmpeq (insn, operands);"
[(set_attr "length" "4")])
--- 8349,8355 ----
(ior:SI (reg:SI T_REG)
(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
! "TARGET_SH2E && TARGET_IEEE && ! TARGET_SH4"
"* return output_ieee_ccmpeq (insn, operands);"
[(set_attr "length" "4")])
***************
*** 8418,8424 ****
[(set (reg:SI T_REG)
(compare (match_operand:SF 0 "arith_operand" "")
(match_operand:SF 1 "arith_operand" "")))]
! "TARGET_SH3E || TARGET_SHMEDIA_FPU"
"
{
sh_compare_op0 = operands[0];
--- 8421,8427 ----
[(set (reg:SI T_REG)
(compare (match_operand:SF 0 "arith_operand" "")
(match_operand:SF 1 "arith_operand" "")))]
! "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
sh_compare_op0 = operands[0];
***************
*** 8429,8438 ****
(define_expand "negsf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
! "TARGET_SH3E || TARGET_SHMEDIA_FPU"
"
{
! if (TARGET_SH3E)
{
expand_sf_unop (&gen_negsf2_i, operands);
DONE;
--- 8432,8441 ----
(define_expand "negsf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
! "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
! if (TARGET_SH2E)
{
expand_sf_unop (&gen_negsf2_i, operands);
DONE;
***************
*** 8450,8456 ****
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
! "TARGET_SH3E"
"fneg %0"
[(set_attr "type" "fmove")
(set_attr "fp_mode" "single")])
--- 8453,8459 ----
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
! "TARGET_SH2E"
"fneg %0"
[(set_attr "type" "fmove")
(set_attr "fp_mode" "single")])
***************
*** 8487,8496 ****
(define_expand "abssf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
! "TARGET_SH3E || TARGET_SHMEDIA_FPU"
"
{
! if (TARGET_SH3E)
{
expand_sf_unop (&gen_abssf2_i, operands);
DONE;
--- 8490,8499 ----
(define_expand "abssf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
! "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
! if (TARGET_SH2E)
{
expand_sf_unop (&gen_abssf2_i, operands);
DONE;
***************
*** 8508,8514 ****
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
! "TARGET_SH3E"
"fabs %0"
[(set_attr "type" "fmove")
(set_attr "fp_mode" "single")])
--- 8511,8517 ----
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
! "TARGET_SH2E"
"fabs %0"
[(set_attr "type" "fmove")
(set_attr "fp_mode" "single")])
***************
*** 9143,9149 ****
(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
(set (mem:SF (match_dup 0))
(match_operand:SF 2 "general_movsrc_operand" ""))]
! "TARGET_SH3E && REGNO (operands[0]) == 0
&& ((GET_CODE (operands[2]) == REG
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
|| (GET_CODE (operands[2]) == SUBREG
--- 9146,9152 ----
(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
(set (mem:SF (match_dup 0))
(match_operand:SF 2 "general_movsrc_operand" ""))]
! "TARGET_SH2E && REGNO (operands[0]) == 0
&& ((GET_CODE (operands[2]) == REG
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
|| (GET_CODE (operands[2]) == SUBREG
***************
*** 9157,9163 ****
(set (match_operand:SF 2 "general_movdst_operand" "")
(mem:SF (match_dup 0)))]
! "TARGET_SH3E && REGNO (operands[0]) == 0
&& ((GET_CODE (operands[2]) == REG
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
|| (GET_CODE (operands[2]) == SUBREG
--- 9160,9166 ----
(set (match_operand:SF 2 "general_movdst_operand" "")
(mem:SF (match_dup 0)))]
! "TARGET_SH2E && REGNO (operands[0]) == 0
&& ((GET_CODE (operands[2]) == REG
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
|| (GET_CODE (operands[2]) == SUBREG
Index: gcc/config/sh/sh64.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh64.h,v
retrieving revision 1.5
diff -c -3 -p -w -r1.5 sh64.h
*** gcc/config/sh/sh64.h 28 May 2002 22:26:43 -0000 1.5
--- gcc/config/sh/sh64.h 23 Jan 2003 18:26:39 -0000
***************
*** 1,5 ****
/* Definitions of target machine for GNU compiler for SuperH SH 5.
! Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
Contributed by Alexandre Oliva <aoliva@redhat.com>
This file is part of GNU CC.
--- 1,5 ----
/* Definitions of target machine for GNU compiler for SuperH SH 5.
! Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
Contributed by Alexandre Oliva <aoliva@redhat.com>
This file is part of GNU CC.
*************** Boston, MA 02111-1307, USA. */
*** 35,41 ****
#define LINK_DEFAULT_CPU_EMUL "32"
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT (SH5_BIT|SH4_BIT|SH3E_BIT|TARGET_ENDIAN_DEFAULT)
#undef SH_ELF_WCHAR_TYPE
#define SH_ELF_WCHAR_TYPE "int"
--- 35,41 ----
#define LINK_DEFAULT_CPU_EMUL "32"
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT (SH5_BIT|SH4_BIT|SH_E_BIT|TARGET_ENDIAN_DEFAULT)
#undef SH_ELF_WCHAR_TYPE
#define SH_ELF_WCHAR_TYPE "int"
Index: gcc/config/sh/t-sh
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/t-sh,v
retrieving revision 1.14
diff -c -3 -p -w -r1.14 t-sh
*** gcc/config/sh/t-sh 18 Jun 2002 19:56:54 -0000 1.14
--- gcc/config/sh/t-sh 23 Jan 2003 18:26:39 -0000
*************** fp-bit.c: $(srcdir)/config/fp-bit.c
*** 31,39 ****
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
MULTILIB_ENDIAN = ml
! MULTILIB_OPTIONS= $(MULTILIB_ENDIAN) m2/m3e/m4-single-only/m4-single/m4
MULTILIB_DIRNAMES=
! MULTILIB_MATCHES = m2=m3 m2=m4-nofpu
MULTILIB_EXCEPTIONS = ml
LIBGCC = stmp-multilib
--- 31,39 ----
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
MULTILIB_ENDIAN = ml
! MULTILIB_OPTIONS= $(MULTILIB_ENDIAN) m2/m2e/m4-single-only/m4-single/m4
MULTILIB_DIRNAMES=
! MULTILIB_MATCHES = m2=m3 m2e=m3e m2=m4-nofpu
MULTILIB_EXCEPTIONS = ml
LIBGCC = stmp-multilib
Index: gcc/doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.226
diff -c -3 -p -w -r1.226 invoke.texi
*** gcc/doc/invoke.texi 23 Jan 2003 10:14:34 -0000 1.226
--- gcc/doc/invoke.texi 23 Jan 2003 18:26:57 -0000
*************** in the following sections.
*** 557,563 ****
@emph{SH Options}
@gccoptlist{
! -m1 -m2 -m3 -m3e @gol
-m4-nofpu -m4-single-only -m4-single -m4 @gol
-m5-64media -m5-64media-nofpu @gol
-m5-32media -m5-32media-nofpu @gol
--- 557,563 ----
@emph{SH Options}
@gccoptlist{
! -m1 -m2 -m2e -m3 -m3e @gol
-m4-nofpu -m4-single-only -m4-single -m4 @gol
-m5-64media -m5-64media-nofpu @gol
-m5-32media -m5-32media-nofpu @gol
*************** Generate code for the SH1.
*** 8759,8764 ****
--- 8759,8767 ----
@item -m2
@opindex m2
Generate code for the SH2.
+
+ @item -m2e
+ Generate code for the SH2e.
@item -m3
@opindex m3