Re: itanium-branch

[Vladimir Makarov <vmakarov at redhat dot com>]

David Edelsohn wrote:
> 
> >>>>> Vladimir Makarov writes:
> 
> Vlad> The most of work is done by the DFA pipeline hazard recognizer.
> Vlad> Although SCHED_REODER(,2) are still used.  But they are simplified
> Vlad> considerably in comparison with NON-DFA scheduler.  They are dealing
> Vlad> mainly with stop bits because the stop bits are defined by dependencies
> Vlad> (data delays) and this information can not be gotten from any pipeline
> Vlad> description which concerns about reservation delays.  The stop bits are
> Vlad> described in the pipeline description but to form EPIC packets we just
> Vlad> need to know where the stop bits should be placed.  It is a bit
> Vlad> complicated because the stop bits are inserted only after 1st and 2nd
> Vlad> insn scheduling.
> 
>         The IBM Power4 does not have stop bits, but it does have
> complicated dispatch requirements which need to be satisfied for optimal
> performance.  SCHED_REORDER(,2) do not seem the right place to form the
> Power4 dispatch groups, but a DFA description appears to be too
> complicated for the current automata generator (although it is much
> smaller than the description on the itanium-branch).  The Power4 dispatch
> groups are more flexible than the EPIC packets, which creates less strict
> dispatch packet formation.
> 
>         Any suggestions for how to deal with this problem?

If I needed do it, I'd definitely use DFA (more correctly NDFA) for
this.  It is not complicated to me.  I saved a lot of my time describing
Itanium2 (after having infrastructure for VLIW packing and scheduling
for Itanium1).  What I needed was only Itanium2 description.  If I used
the old approach, I'd spend ten times more time and the code dealing
with Itanium2 beside Itanium1 would be really not readable.

  What alternative do we have?  To get good insn scheduling, scheduler
should have information about VLIW packing (Power4 groups).  So we
should describe the information for the scheduler by old pipeline
description or DFA one.  The old pipeline description is not powerful
for this therefore we need use machine-dependent code called through
hooks (SHED_REORDER etc).  In this case we could have the same
complicated code which we had (or have on the mainline) for Itanium1. 
So I don't see alternative to DFA scheduler here.

The task could be simplified (I think you mean it) if we have different
phase for group dispatching.  Well in that case the insn scheduling will
be worse.

Vlad