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mn10300: fixed and improved bit patterns
- From: Alexandre Oliva <aoliva at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: 13 Dec 2002 21:06:17 -0200
- Subject: mn10300: fixed and improved bit patterns
- Organization: GCC Team, Red Hat
This patch fixes problems that were introduced back when we started
enforcing the sign-extension of constants, that caused QImode
constants such as -128 to be rejected by the assembler when it needed
an unsigned 8-bit constant. Also, at some point combine stopped being
able to turn a sequence of QImode load, ior/and, store (in which mems
have been forced into registers by -fforce-mem) into a single
bclr/bset instruction in certain cases, so I introduced a few more
patterns to make it happy. Tested with
i686-pc-linux-gnu-x-mn10300-elf. I'm checking this in.
Index: gcc/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
* config/mn10300/mn10300.c (print_operand) <case N>: Check
operand's range. Print value directly, without aid from
output_address.
<case U>: New.
<case S>: Make sure argument to fprintf has the right type.
* config/mn10300/mn10300.h (OK_FOR_T): New macro.
(EXTRA_CONSTRAINT): Adjust.
* config/mn10300/mn10300.md: Add new all-QImode pattern for
bclr. Use %U for immediate operands of bset and bclr.
(iorqi3): New expand, with insns for AM33 and mn10300.
Index: gcc/config/mn10300/mn10300.c
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mn10300/mn10300.c,v
retrieving revision 1.45
diff -u -p -r1.45 mn10300.c
--- gcc/config/mn10300/mn10300.c 15 Sep 2002 18:24:07 -0000 1.45
+++ gcc/config/mn10300/mn10300.c 13 Dec 2002 21:49:19 -0000
@@ -1,5 +1,5 @@
/* Subroutines for insn-output.c for Matsushita MN10300 series
- Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001
+ Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002
Free Software Foundation, Inc.
Contributed by Jeff Law (law@cygnus.com).
@@ -264,7 +264,15 @@ print_operand (file, x, code)
break;
case 'N':
- output_address (GEN_INT ((~INTVAL (x)) & 0xff));
+ if (INTVAL (x) < -128 || INTVAL (x) > 255)
+ abort ();
+ fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
+ break;
+
+ case 'U':
+ if (INTVAL (x) < -128 || INTVAL (x) > 255)
+ abort ();
+ fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
break;
/* For shift counts. The hardware ignores the upper bits of
@@ -274,7 +282,7 @@ print_operand (file, x, code)
case 'S':
if (GET_CODE (x) == CONST_INT)
{
- fprintf (file, "%d", INTVAL (x) & 0x1f);
+ fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
break;
}
/* FALL THROUGH */
Index: gcc/config/mn10300/mn10300.h
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mn10300/mn10300.h,v
retrieving revision 1.64
diff -u -p -r1.64 mn10300.h
--- gcc/config/mn10300/mn10300.h 20 Aug 2002 23:27:03 -0000 1.64
+++ gcc/config/mn10300/mn10300.h 13 Dec 2002 21:49:20 -0000
@@ -678,9 +678,17 @@ struct cum_arg {int nbytes; };
&& GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT \
&& INT_8_BITS (INTVAL (XEXP (XEXP (OP, 0), 1))))))
+#define OK_FOR_T(OP) \
+ (GET_CODE (OP) == MEM \
+ && GET_MODE (OP) == QImode \
+ && (GET_CODE (XEXP (OP, 0)) == REG \
+ && REG_OK_FOR_BIT_BASE_P (XEXP (OP, 0)) \
+ && XEXP (OP, 0) != stack_pointer_rtx))
+
#define EXTRA_CONSTRAINT(OP, C) \
((C) == 'R' ? OK_FOR_R (OP) \
: (C) == 'S' ? GET_CODE (OP) == SYMBOL_REF \
+ : (C) == 'T' ? OK_FOR_T (OP) \
: 0)
/* Maximum number of registers that can appear in a valid memory address. */
Index: gcc/config/mn10300/mn10300.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/mn10300/mn10300.md,v
retrieving revision 1.43
diff -u -p -r1.43 mn10300.md
--- gcc/config/mn10300/mn10300.md 3 May 2001 18:41:29 -0000 1.43
+++ gcc/config/mn10300/mn10300.md 13 Dec 2002 21:49:21 -0000
@@ -1,5 +1,5 @@
;; GCC machine description for Matsushita MN10300
-;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001
+;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002
;; Free Software Foundation, Inc.
;; Contributed by Jeff Law (law@cygnus.com).
@@ -1258,16 +1258,65 @@
[(set_attr "cc" "clobber,set_znv")])
(define_insn ""
+ [(set (match_operand:QI 0 "memory_operand" "=R,T")
+ (and:QI
+ (match_dup 0)
+ (not:QI (match_operand:QI 1 "nonmemory_operand" "i,d"))))]
+ ""
+ "@
+ bclr %U1,%A0
+ bclr %1,%0"
+ [(set_attr "cc" "clobber,clobber")])
+
+(define_insn ""
[(set (match_operand:QI 0 "nonimmediate_operand" "+R,d")
(subreg:QI
(ior:SI (subreg:SI (match_dup 0) 0)
(match_operand:SI 1 "const_int_operand" "i,i")) 0))]
""
"@
- bset %1,%A0
+ bset %U1,%A0
or %1,%0"
[(set_attr "cc" "clobber,set_znv")])
+(define_expand "iorqi3"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "")
+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=R,T,r")
+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
+ ;; This constraint should really be nonmemory_operand,
+ ;; but making it general_operand, along with the
+ ;; condition that not both input operands are MEMs, it
+ ;; here helps combine do a better job.
+ (match_operand:QI 2 "general_operand" "i,d,ir")))]
+ "TARGET_AM33 &&
+ (GET_CODE (operands[2]) != MEM || GET_CODE (operands[1]) != MEM)"
+ "@
+ bset %U2,%A0
+ bset %2,%0
+ or %2,%0"
+ [(set_attr "cc" "clobber,clobber,set_znv")])
+
+(define_insn ""
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=R,T,d")
+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
+ ;; This constraint should really be nonmemory_operand,
+ ;; but making it general_operand, along with the
+ ;; condition that not both input operands are MEMs, it
+ ;; here helps combine do a better job.
+ (match_operand:QI 2 "general_operand" "i,d,id")))]
+ "GET_CODE (operands[2]) != MEM || GET_CODE (operands[1]) != MEM"
+ "@
+ bset %U2,%A0
+ bset %2,%0
+ or %2,%0"
+ [(set_attr "cc" "clobber,clobber,set_znv")])
+
(define_insn ""
[(set (cc0)
(zero_extract:SI (match_operand:SI 0 "register_operand" "dx")
@@ -1335,7 +1384,7 @@
if (GET_CODE (operands[0]) == REG)
output_asm_insn (\"btst %1,%0\", xoperands);
else
- output_asm_insn (\"btst %1,%A0\", xoperands);
+ output_asm_insn (\"btst %U1,%A0\", xoperands);
return \"\";
}"
[(set_attr "cc" "clobber")])
@@ -1354,7 +1403,7 @@
(match_operand:SI 1 "const_8bit_operand" "")))]
""
"@
- btst %1,%A0
+ btst %U1,%A0
btst %1,%0"
[(set_attr "cc" "clobber")])
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{redhat.com, gcc.gnu.org}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist Professional serial bug killer