[PATCH] Fix SH Interrupt Handler ICE

["Dhananjay R. Deshpande" <dhananjayd at kpit dot com>]

Hi,

Following code compiled with sh-elf-gcc -c isr.c gives ICE.

----------------- isr.c ------------------------------------------------
extern void foo();

#pragma interrupt
void  isr1(void)
{
        foo();
}
------------------------------------------------------------------------

isr.c: In function `isr1':
isr.c:6: insn does not satisfy its constraints:
(insn 40 39 41 (set (reg:SI 151 fpscr)
        (mem:SI (post_inc:SI (reg/f:SI 15 r15)) [0 S4 A32])) 112 {movsi_i} (nil)
    (expr_list:REG_INC (reg/f:SI 15 r15)
        (nil)))
isr.c:6: Internal compiler error in extract_constrain_insn_cached, at recog.c:2063
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://www.gnu.org/software/gcc/bugs.html> for instructions.

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I think the patch that has caused this problem is 
http://gcc.gnu.org/ml/gcc-patches/2002-08/msg01648.html


The ICE occurs for targets which don't have FPU as well as targets with FPU.

The call insn has "use fpscr" so interrupt handler sees FPSCR as live on all 
targets and there are no push/pop patterns in sh.md for FPSCR.

The patch below adds push/pop patterns and generates respective RTX when 
REG = FPSCR_REG in push() and pop(). In calc_live_regs(), it saves FPSCR only 
for targets having FPU.

Regards,
Dhananjay

Changelog :- 
2002-11-29 Dhananjay Deshpande <dhananjayd@kpit.com>
	* gcc/config/sh/sh.c (calc_live_regs): Save fpscr only if target has FPU
	  (push): Generate push_fpscr RTX 
	  (pop): Generate pop_fpscr RTX
	* gcc/config/sh/sh.md : Add push_fpscr and pop_fpscr patterns

===============================================================================

--- gcc/config/sh.old/sh.c	Tue Nov 19 14:29:29 2002
+++ gcc/config/sh/sh.c	Mon Nov 25 11:35:38 2002
@@ -4319,6 +4319,8 @@ push (rn)
   rtx x;
   if (rn == FPUL_REG)
     x = gen_push_fpul ();
+  else if (rn == FPSCR_REG)
+    x = gen_push_fpscr ();
   else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
 	   && FP_OR_XD_REGISTER_P (rn))
     {
@@ -4347,6 +4349,8 @@ pop (rn)
   rtx x;
   if (rn == FPUL_REG)
     x = gen_pop_fpul ();
+  else if (rn == FPSCR_REG)
+    x = gen_pop_fpscr ();
   else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
 	   && FP_OR_XD_REGISTER_P (rn))
     {
@@ -4445,7 +4449,9 @@ calc_live_regs (count_ptr, live_regs_mas
 		  && pr_live))
 	     && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
 	     && reg != RETURN_ADDRESS_POINTER_REGNUM
-	     && reg != T_REG && reg != GBR_REG)
+	     && reg != T_REG && reg != GBR_REG
+	     /* Push fpscr only on targets which have FPU */
+	     && (TARGET_FPU_ANY || reg != FPSCR_REG))
 	  : (/* Only push those regs which are used and need to be saved.  */
 	     (TARGET_SHCOMPACT
 	      && flag_pic

===============================================================================

--- gcc/config/sh.old/sh.md	Tue Nov 19 14:29:29 2002
+++ gcc/config/sh/sh.md	Mon Nov 25 11:28:09 2002
@@ -3308,6 +3308,14 @@
    (set_attr "late_fp_use" "yes")
    (set_attr "hit_stack" "yes")])
 
+(define_insn "push_fpscr"
+  [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPSCR_REG))]
+  "(TARGET_SH3E) && ! TARGET_SH5"
+  "sts.l	fpscr,@-r15"
+  [(set_attr "type" "store")
+   (set_attr "late_fp_use" "yes")
+   (set_attr "hit_stack" "yes")])
+
 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
 ;; so use that.
 (define_expand "push_4"
@@ -3330,6 +3338,13 @@
   [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
   "TARGET_SH3E && ! TARGET_SH5"
   "lds.l	@r15+,fpul"
+  [(set_attr "type" "load")
+   (set_attr "hit_stack" "yes")])
+
+(define_insn "pop_fpscr"
+  [(set (reg:SF FPSCR_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
+  "(TARGET_SH3E) && ! TARGET_SH5"
+  "lds.l	@r15+,fpscr"
   [(set_attr "type" "load")
    (set_attr "hit_stack" "yes")])
 
===============================================================================

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